N-doped graphene with low intrinsic defect densities was obtained by combining a solid source doping technique and chemical vapor deposition (CVD). The solid source for N-doping was embedded into the copper substrate by NH₃ plasma immersion. During the treatment, NH₃ plasma radicals not only flattened the Cu substrate such that the root-mean-square roughness value gradually decreased from 51.9 nm to 15.5 nm but also enhanced the nitrogen content in the Cu substrate. The smooth surface of copper enables good control of graphene growth and the decoupling of height fluctuations and ripple effects, which compensate for the Coulomb scattering by nitrogen incorporation. On the other hand, the nitrogen atoms on the pre-treated Cu surface enable nitrogen incorporation with low defect densities, causing less damage to the graphene structure during the process. Most incorporated nitrogen atoms are found in the pyrrolic configuration, with the nitrogen fraction ranging from 1.64% to 3.05%, while the samples exhibit low defect densities, as revealed by Raman spectroscopy. In the top-gated graphene transistor measurement, N-doped graphene exhibits n-type behavior, and the obtained carrier mobilities are greater than 1100 cm²·V⁻¹·s⁻¹. In this study, an efficient and minimally damaging n-doping approach was proposed for graphene nanoelectronic applications.

In this article, a novel high robust and latch-up immune electrostatic discharge (ESD) protection device, called gate-controlled low-voltage-triggered silicon-controlled rectifier (GC-LVTSCR), is proposed for 5-V I/O protection applications in the advance 40-nm CMOS technology. By incorporating a surface current diverting path with a controlling poly-silicon gate (CG) into the conventional LVTSCR, the GC-LVTSCR’s ESD characteristics can be improved and modulated with two bias conditions of CG. The first improved GC-LVTSCR structure named gate-to-body SCR (GBSCR) with the CG tied to the PWell’s body is expected to realize higher holding voltage ( $\textit{V}_{\text{h}}\text{)}$ and lower trigger voltage ( $\textit{V}_{\text{t\text{1}}}\text{)}$ , while the other structure named gate-to-drain SCR (GDSCR) using the CG connected to the bridging p $+$ region of LVTSCR is designed to gain even higher $\textit{V}_{\text{h}}$ . Measurement results show that the GBSCR has $\sim$ 11% lowered $\textit{V}_{\text{t\text{1}}}$ , $\sim$ 38% enhanced $\textit{V}_{\text{h}}$ , and improved charged device model (CDM) characteristics by comparing with the traditional LVTSCR, and the GDSCR possesses a further improved $\textit{V}_{\text{h}}$ with $\sim$ 45% higher than the GBSCR. Besides, the new devices are expected to protect 5 V or above I/O in submicrometer technologies and have been realized in a 0.18- $\mu $ m BCD process.

In this brief, two novel diode-triggered silicon-controlled rectifiers (DTSCRs) with fast turn-on speed have been presented. By embedding current gain amplifier modules (i.e., Sziklai pair and Darlington pair) into the conventional DTSCR, the current gain of parasitic bipolar junction transistors (BJTs) on the silicon-controlled rectifier (SCR) path in the new devices becomes much larger than that of the conventional counterpart, thus resulting in a faster turn-on speed and better quasi-static ${I}$ – ${V}$ characteristics. As such, the quasi-static triggering characteristic of the new DTSCR improves by 80%, and the turn-on speed improves by 42%–93% for different current levels.

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current ( ${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$ . Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation.

In this paper, an enhanced modified lateral silicon-controlled rectifier (EMLSCR) has been proposed and demonstrated. Compared with the traditional MLSCR, the EMLSCR possesses a lower trigger voltage of 7.0 V as well as a higher robustness, making it very suitable for the electrostatic discharge (ESD) protection for 2.5-V/3.3-V/5-V IOs in the advanced 65-nm epitaxial CMOS technology. Additionally, an improved transmission line pulsing (TLP) measurement strategy by adopting TLP pulses with various rise time has been put forward to provide a convenient and economical approach to explore the conduction uniformity of the ESD device for the first time. Furthermore, two optimization methods are proposed and evaluated to overcome the prefailure issue due to the small well resistance inherited in the EPI process as well. The method of well pickup segmentation is demonstrated to be more efficient since it could increase the well resistance and augment the effective emitter area of parasitic bipolar junction transistors (BJTs) under constant device area.