This paper presents a novel quarter-mode packaged bandpass filter with four transmission zeros (TZs) in substrate-integrated waveguide (SIW) technology. The filter has an insertion loss of 2.85 dB at 30 GHz and fractional bandwidth of 20%. The design methodology of the TZs was first demonstrated to increase the attenuations of the filter stopband. The quarter-mode SIW resonators were analyzed with high-mode suppression by properly setting their feed points. The packaged filter was consistent between the simulation and measurement results and offers the advantages of compact configuration and easy integration with other devices. Mode suppressions of up to 110 GHz were also provided. The proposed concept is attractive for designing miniaturized and high-performance-packaged filters for 3-D millimeter-wave transceiver systems.

This paper suggests the usage of an optimized structure of the embedded wafer-level ball grid array technology for millimeter-wave antennas-in-package. Multiple antenna arrays in a second redistribution layer have been designed, evaluated, and integrated with different transceivers to form very compact sensor packages for 61- and 122-GHz radar applications. The resulting packages contain a complete radar front end while featuring dimensions of $8 mmx 8$ mm. The packages are easy to assemble and replaceable. Theoretical considerations, numerical results, and measurements have been carried out for the single components. For the verification of the sensor packages, a system demonstrator was developed, and measurements have been performed in continuous-wave mode. At both frequencies, promising system performance regarding range and distance errors could be confirmed without the usage of complex processing and calibration algorithms.

In this work, we present an integrated read and programming circuit for Resistive Random Access Memory (RRAM) cells. Since there are a lot of different RRAM technologies in research and the process variations of this new memory technology often spread over a wide range of electrical properties, the proposed circuit focuses on versatility in order to be adaptable to different cell properties. The circuit is suitable for both read and programming operations based on voltage pulses of flexible length and height. The implemented read method is based on evaluating the voltage drop over a measurement resistor and can distinguish up to eight different states, which are coded in binary, thereby realizing a digitization of the analog memory value. The circuit was fabricated in the 130 nm CMOS process line of IHP. The simulations were done using a physics-based, multi-level RRAM model. The measurement results prove the functionality of the read circuit and the programming system and demonstrate that the read system can distinguish up to eight different states with an overall resistance ratio of 7.9.