This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance C_L varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.

This article presents a dual-output switched-capacitor (DOSC) dc-dc regulator to support hundreds-of-milliampere load per output. To save chip and board areas, the regulator adopts an all-nMOS auto-configurable power stage and generates two different output voltages via sharing flying capacitors and power transistors. In the controller, a continuous gate-drive modulation (CGDM) scheme is proposed to minimize the output cross regulation when one output undergoes large load step changes. A small output voltage ripple is also achieved at each output by the CGDM with only a small capacitance of 2.2 μF/output under heavy-load conditions. Implemented in a standard 0.13-μm CMOS process, the proposed regulator generates two regulated outputs of 0.8 V and 1.6 V from the input of 2.7-4.2 V. It supports a maximum load of 600 mA/output, provides a low output ripple of ≤ 20 mV with the CGDM, and achieves a peak power efficiency of 89.5%. The output cross regulation is only 0.01 mV/mA under large load step changes of 580 mA. Compared with state-of-the-art SIMO dc-dc converters, the proposed work achieves >4x reduction in the output cross regulation under >2x larger load step changes and >2x smaller load capacitance/output.

This article presents a wide-input-range low-profile dc-dc-based LED driver. An adaptive delay compensated hysteretic control (ADCHC) is proposed to adaptively modulate both peak and valley inductor currents for minimizing their current deviations, thereby enhancing the accuracy of the average LED current under different input and output voltages. A high-voltage current sensor with passive ripple filtering scheme is also developed to ensure fast and accurate inductor current sensing in the megahertz (MHz) range. The proposed LED driver was realized using two 100-V e-mode GaN FETs as power switches together with on-chip gate drivers and controller implemented in a 0.5-μm, 120-V process. This driver supports an input voltage range from 5 to 100 V and delivers a maximum output power of 25 W. The LED current error is minimized to within ±3.2% of the nominal 350-mA LED current under different input voltages and numbers of output LEDs. Compared with the prior art, the proposed LED driver has the smallest LED current error, operates 2 times higher frequency, and uses 5x and 5.5x smaller inductance and inductor volume. The proposed LED driver also features competitive peak power efficiency of 91.7% at 1.8-MHz frequency and 90-V input.

This article presents a dc–dc bus converter with a new soft-switching scheme. Adaptive zero-voltage transition (AZVT) is proposed to enable ZVS turn-on of the power FET via a ZVT auxiliary branch for removing the switching loss of the converter. In AZVT, the current of the auxiliary branch is discontinuous and its peak value is controlled to decrease with the load current. This feature not only minimizes the conduction loss of the auxiliary branch but also significantly improves the light-load power efficiency of the converter. In addition, a high-voltage flipped current sensor (HVFCS) is developed to enable fast and accurate auxiliary inductor current sensing for supporting proper AZVT control in the MHz range. The proposed converter was validated using three 100-V e-mode GaN FETs together with the proposed AZVT controller and gate drivers implemented in a 0.5- $\mu \text{m}$ , 120-V CMOS process. The proposed AZVT converter supports a wide input range from 48 to 80 V, operates at 2 MHz, and provides the power efficiency improvements up to 14.5% and 8.7% over the hard-switching operation at the input voltages of 48 and 80 V, respectively. Compared with the state-of-the-art designs, the proposed converter not only obtains >90% power efficiency over a load range of 6–60 W but also improves light-load efficiency by over 5% with more than two times higher switching frequency.