This paper presents a novel maximum efficiency point (MEP) tracking method for wireless power transfer (WPT) systems. It is proved that at the MEP for a typical system containing a boost converter on the receiving end, the derivative dD/dV _in (V _in being the inverter's dc input and D being the duty cycle of the converter) is equal to or smaller than a constant β that is determined by system parameters. By tuning V _in and comparing dD/dV _in with β, the MEP can be tracked without a power or current sensor, hence reducing the tracking cost. A WPT system is demonstrated experimentally to verify the method. When the diameters of and the vertical distance between the transmitting and receiving coils are 4.3 and 2.35 cm, respectively, without horizontal misalignment, high efficiency is maintained even when the load ranges from 5 to 100 Ω, and the efficiency improvement reaches 41.2% when compared to the measured efficiencies without the proposed method. The differences between the maximum efficiencies tracked by the proposed method and the manually searched maximum values are at most 1.8%. Extension of the proposed method to WPT systems employing other popular forms of inverter, dc/dc converter, and coil topology is also presented.

This manuscript presents an ultra-low power acoustic feature extractor for always-on voice activity detection (VAD). It extracts voice features by a 10-band passive switched-capacitor (SC) bandpass filter (BPF) bank and digitizes the features using a passive SC envelope-to-digital converter at the low feature rate. The SC feature extractor minimizes the impact of process-voltage-temperature (PVT) variation at the circuit level, and is thereby free from costly chip-wise training or calibration while at the same time being capable of achieving a classification accuracy matching the state of the arts. Experimental results from a VAD feature extractor prototype fabricated in a 0.18-μm CMOS validate the effectiveness of the proposed techniques. It achieves an averaged 90%/86% speech/non-speech hit rates at 10 dB signal-to-noise ratio for all tested chips based on a universal classifier trained with data from one chip. The feature extractor is mostly passive and thus a low power consumption of 270 nW is achieved. In addition, the proposed feature extractor is frequency-scalable, which allows power-efficient multi-purpose acoustic system implementation.

This paper presents a new frequency compensation approach for three-stage amplifiers driving a pF-to-nF capacitive load. Thanks to the cascode Miller compensation, the non-dominant complex pole frequency is extended effectively, and the physical size of the compensation capacitors is also reduced. A local Q-factor control (LQC) loop is introduced to alter the Q-factor adaptively when loading capacitance C_L varies significantly. This LQC loop decides how much damping current should be injected into the corresponding parasitic node to control the Q-factor of the complex-pole pair, which affects the frequency peak at the gain plot and the settling time of the proposed amplifier in the closed-loop step response. Additionally, a left-half-plane (LHP) zero is created to increase the phase margin and a feed-forward transconductance stage is paralleled to improve the slew rate (SR). Simulated in 0.13-µm CMOS technology, the amplifier is verified to handle a 4-pF-to-1.5-nF (375× drivability) capacitive load with at least 0.88-MHz gain-bandwidth (GBW) product and 42.3° phase margin (PM), while consuming 24.0-µW quiescent power at 1.0-V nominal supply voltage.

This paper presents a low-power high-accuracy key-word spotting (KWS) system based on analog passive switched-capacitor (SC) bandpass filters (BPF). The proposed system inno-vatively extracts the Mel-frequency cepstrum coefficient (MFCC) features with all-analog circuits, providing a better spotting performance than the present analog short-time amplitude or energy features under the same condition. At the circuit level, the analog-MFCC extraction includes the low-noise amplifier, BPF, squarer, integrator, and discrete cosine transformer. And thanks to the effective analog-MFCC features, the size of the fully-connected neural network (FCNN) classifier in our KWS system is enormously reduced. A high-order and fully-differential BPF is also proposed, achieving ultra-low power and high dynamic range by combining zero and pole generation stages rather than building stages separately in traditional ways. Fabricated in 0.18- $\mu \text{m}$ CMOS, our filterbank of eight BPFs is measured with a power consumption of 83.2 nW, with a 69.7 dB dynamic range at 5% THD, having advantages over other SC BPFs with similar functions. The total power consumption of our feature extractor is 661.7 nW, achieving an accuracy of 96.6% in two-keyword spotting by an FPGA-based, 15k bit parameter FCNN with a 9.6 $\mu \text{s}$ latency.