As the most popular wide bandgap (WBG) power device, the silicon carbide (SiC) MOSFET has been widely adopted in the power electronics applications, and brings in the benefits including reduced switching losses, enhanced switching frequency, and improved power density. However, the switching oscillation and the electromagnetic interference (EMI) become more serious due to the rapid switching speed of SiC MOSFET. Thus, adding RC snubber branch is considered as an effective method to suppress such unwanted oscillation in the early works. In this paper, the switching transient of SiC MOSFET with RC snubber is investigated with an analytical model based on finite state machine (FSM). The accuracy of proposed analytical model can be verified by comparisons between calculated and measured waveforms during the switching transition. In addition, the impacts of the RC snubber on switching oscillation, switching loss and high-frequency (HF) EMI noise have been comprehensively investigated based on the model, which shows that the added RC snubber can effectively avoid the switching oscillation, and reduce the level of HF EMI without increasing switching loss.

Permanent magnet synchronous motor (PMSM) has been widely applied in a pulse width modulation inverter‐fed adjustable speed drive (ASD) system. However, electromagnetic interference (EMI) has become a critical issue in such a system. Plenty of high‐frequency harmonic components, generated by high d v /d t or d i /d t of the modern transistors, can be observed on the line‐to‐line voltage across motor terminals. To study the conducted EMI issues existed in the ASD system, an improved model of PMSM is developed to represent the high‐frequency behaviour, and the equivalent circuit parameters for common mode (CM) and differential mode (DM) are extracted based on the measurements. The model calculated CM and DM impedances are in good agreement with the measured ones from the impedance analyser, which verifies the effectiveness of the proposed high‐frequency model.

Gallium Nitride (GaN) High Electron Mobility Transistor (HEMT) is a promising candidate for the high-density power converter applications. Due to the low switching loss, the GaN HEMT may lead to a new horizon in the applications such as fast charger, wireless charging, and 5G power amplifier. However, the fast switching speed of GaN HEMT makes it extremely sensitive to parasitic parameters, especially for the low-voltage GaN devices with small packages. Conventional switching loss estimation methods, which are normally based on the calibration fixture or modification of test circuit, cannot be effectively utilized for GaN HEMT. This paper presents an accurate switching loss estimation method using the post-processing technique. The proposed switching loss technique consists of three parts of signal processing, which are the wavelet denoising process to minimize the influence of background noise, the voltage-current $(V - I)$ alignment process to reduce errors from probe propagation delay, and the linear interpolation process for further improvement of alignment accuracy. In addition, a modified SPICE model is proposed to investigate the influence of parasitic parameters on switching losses by the circuit simulation. Based on the theoretical switching characteristics, the switching loss estimation method is finally validated experimentally on a commercial 40-V/10-A GaN HEMT in a double pulse test.

The accurate measurement of the voltage and current waveforms during the high-speed switching transition of the discrete silicon carbide (SiC) devices is necessary in order to estimate the switching loss with reasonable accuracy. The current measurement is usually more challenging, as it requires the insertion of a current sensor into the testing board. The existing current measuring methods are still limited by the drawbacks, such as low current rating, low bandwidth, and bulky size, for installation. As a result, an in situ current measuring method with convenient installation as well as sufficient current rating and bandwidth are proposed in this article, which consists of a first-stage custom-made current transformer (CT) and followed by a second-stage current probe (CP). By having the custom-made CT, the size of the CT can be very compact and requires little space provision in the testing board, which preserve the measuring accuracy. A comprehensive analytical model with bandwidth, current gain, and saturation current as design parameters is developed. Based on the developed model, three CT designs using different magnetic cores are fabricated and their performances are also experimentally validated.

Short-circuit faults are the most critical failure mechanism in power converters. Among the various short-circuit protection schemes, desaturation protection is the most mature and widely used solution. Due to the lack of gate driver integrated circuit (IC) with desaturation protection for the silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET), the conventional insulated gate bipolar transistor (IGBT) driver IC is normally used as these two devices have similar gate structure and driving mechanism. In this work, a gate driver with desaturation protection is designed for the 1.2-kV/30-A SiC MOSFET and silicon (Si) IGBT with the off-the-shelf driver IC. To further limit voltage-overshoot at the rapid turn-off transient, the active clamping circuit is introduced. Based on the experiments of switching characterization and short-circuit test, the SiC MOSFET shows faster switching speed, more serious electromagnetic interference (EMI) issue, lower switching loss (half), and higher short-circuit current (1.6 times) than the Si IGBT, even with a slower gate driver. Thus, a rapid response speed is required for the desaturation protection circuit of SiC MOSFET. Due to the long delay time of the existing desaturation protection scheme, it is technically difficult to design a sub- $\mathsf{\mu }$ s protection circuit. In this work, an external current source is proposed to charge the blanking capacitor. A short-circuit time of 0.91 $\mathsf{\mu }$ s is achieved with a reliable protection. Additionally, the peak current is reduced by 22%.

The silicon carbide (SiC) power module is one of the most popular semiconductor devices in industrial applications with the enhanced current rating. In this paper, a 1200-V/200-A SiC three-level (3L) module with neutral point clamped (NPC) topology is designed and validated. Compared with other existing works, the drain current of the designed module is accurately measured by a custom-made current transformer (CT) combined with a commercially off-the-shelf current probe (CP), which is critical for power loss evaluation. Based on the simulation and experiment results, it can be found that the maximum internal commutation loop stray inductance is no more than 40 nH, and the total switching loss can be reduced more than 30 $\%$ compared with the hybrid 3L NPC module (Si IGBTs+SiC SBDs). Meanwhile, the power loss evaluation demonstrates that the designed 3L NPC module with all-SiC device is more suitable for high-voltage and high-frequency applications compared with its 2L counterpart, and the thermal simulation shows that the maximum junction temperature is less than 120 ${}^{\circ }$ C when the module operates as a buck converter with $V_{DC}$ = 600 V, $I_{o}$ = 150 A, and $f_{s}$ = 100 kHz. In addition, compared with the 2L module, the 3L one presents enhanced spectrum amplitude in the high frequency (HF) range ( $\ge$ 10 MHz) for the high-voltage applications, which indicates higher electromagnetic interference (EMI) noise. Then, two types of sunbber circuits are used to suppress the HF oscillation of the SiC 3L NPC module and alleviate the EMI noise as well according to the experiment results.