Number theoretic transform (NTT) method shows great advantages in speed and efficiency for applications such as homomorphic encryption. However, the twiddle factor data consumes a lot of memories. In this paper, we propose a novel data compression method, together with the corresponding data storage scheme and addressing algorithm. Furthermore, we design a 768k-bit multiplier with a full pipeline structure. Our proposed compression method has achieved a compression rate of 98.8% for the twiddle factor data. Compared with the state-of-the-art FPGA implementations, our design shows up to 44.2% improvement in terms of area-efficiency.

Binarized neural networks (BNNs) and batch normalization (BN) have already become typical techniques in artificial intelligence today. Unfortunately, the massive accumulation and multiplication in BNN models bring challenges to field-programmable gate array (FPGA) implementations, because complex arithmetics in BN consume too much computing resources. To relax FPGA resource limitations and speed up the computing process, we propose a BNN accelerator architecture based on consolidation compressed tree scheme by combining both XNOR and accumulation operation of the low bit into a systematic one. During the compression process, we adopt 0-padding (not ±1) to achieve no-accuracy-loss from software modeling to hardware implementation. Moreover, we introduce shift-addition-BN free binarization technique to shorten the delay path and optimize on-chip storage. To sum up, we drastically cut down the hardware consumption while maintaining great speed performance with the same model complexity as the previous design. We evaluate our accelerator on MNIST and CIFAR-10 dataset and implement the whole system on the ARTIX-7 100T FPGA with speed performance of 2052.65 GOP/s and area efficiency of 70.15 GOPS/KLUT.

Fully homomorphic encryption has become a key technique for solving the conflict between cloud services and privacy preservation. The most time-consuming step in homomorphic schemes is ring polynomial multiplication (RPM). Number theory transform (NTT) and Karatsuba algorithms are efficient to accelerate RPM, yet they are limited by the modulus operations and degrees of the polynomial. The systolic array is adopted for RPM processing recently. However, a modular reduction operation is required as post-processing which increases the overall delay. This paper has proposed a cyclic systolic array architecture without a dedicated reduction unit by re-routing the output of the systolic array for reusing, resulting in a 50% clock cycles saving of processing time. The corresponding FPGA implementation has a reduction of 72.9% and 33.8% when n=256 and n=1024 for equivalent area time product (eATP), respectively, therefore achieving an improved trade-off between performance and resource consumption.

Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery. Solving the packet reordering problem is one of the keys to ensure the quality of service (QoS) for NoC. However, traditional packet reordering approaches rely on local reorder buffer, causing on-chip hotspots, which aggravates chip aging and even leads to interconnection failures. In this paper, we present a multistage packet reordering (MPR) approach, which cannot only reduce the transmission latency but also effectively reduces hotspots caused by local reordering. Specifically, we propose multistage reordering buffer (MRB) by reusing channel buffers for implementing MPR. Experimental results show that our proposed approach achieved improved thermal efficiency with reduced hardware resource consumption.