The recent explosive compute growth, mainly fueled by the boost of artificial intelligence (AI) and deep neural networks (DNNs), is currently instigating the demand for a novel computing paradigm that can overcome the insurmountable barriers imposed by conventional electronic computing architectures. Photonic neural networks (PNNs) implemented on silicon integration platforms stand out as a promising candidate to endow neural network (NN) hardware, offering the potential for energy efficient and ultra-fast computations through the utilization of the unique primitives of photonics, i.e., energy efficiency, THz bandwidth, and low-latency. Thus far, several demonstrations have revealed the huge potential of PNNs in performing both linear and non-linear NN operations at unparalleled speed and energy consumption metrics. Transforming this potential into a tangible reality for deep learning (DL) applications requires, however, a deep understanding of the basic PNN principles, requirements, and challenges across all constituent architectural, technological, and training aspects. In this Tutorial, we, initially, review the principles of DNNs along with their fundamental building blocks, analyzing also the key mathematical operations needed for their computation in photonic hardware. Then, we investigate, through an intuitive mathematical analysis, the interdependence of bit precision and energy efficiency in analog photonic circuitry, discussing the opportunities and challenges of PNNs. Followingly, a performance overview of PNN architectures, weight technologies, and activation functions is presented, summarizing their impact in speed, scalability, and power consumption. Finally, we provide a holistic overview of the optics-informed NN training framework that incorporates the physical properties of photonic building blocks into the training process in order to improve the NN classification accuracy and effectively elevate neuromorphic photonic hardware into high-performance DL computational settings.

The relentless growth of Artificial Intelligence (AI) workloads has fueled the drive towards non-Von Neuman architectures and custom computing hardware. Neuromorphic photonic engines aspire to synergize the low-power and high-bandwidth credentials of light-based deployments with novel architectures, towards surpassing the computing performance of their electronic counterparts. In this paper, we review recent progress in integrated photonic neuromorphic architectures and analyze the architectural and photonic hardware-based factors that limit their performance. Subsequently, we present our approach towards transforming silicon coherent neuromorphic layouts into high-speed and high-accuracy Deep Learning (DL) engines by combining robust architectures with hardware-aware DL training. Circuit robustness is ensured through a crossbar layout that circumvents insertion loss and fidelity constraints of state-of-the-art linear optical designs. Concurrently, we employ DL training models adapted to the underlying photonic hardware, incorporating noise- and bandwidth-limitations together with the supported activation function directly into Neural Network (NN) training. We validate experimentally the high-speed and high-accuracy advantages of hardware-aware DL models when combined with robust architectures through a SiPho prototype implementing a single column of a 4:4 photonic crossbar. This was utilized as the pen-ultimate hidden layer of a NN, revealing up to 5.93% accuracy improvement at 5GMAC/sec/axon when noise-aware training is enforced and allowing accuracies of 99.15% and 79.8% for the MNIST and CIFAR-10 classification tasks. Channel-aware training was then demonstrated by integrating the frequency response of the photonic hardware in NN training, with its experimental validation with the MNIST dataset revealing an accuracy increase of 12.93% at a record-high rate of 25GMAC/sec/axon.

We demonstrate a novel interferometric coherent photonic crossbar architecture (Xbar) that can realize any tensor operator and allows for total loss-induced fidelity restoration, offering at the same time significant dimension scalability credentials compared to respective state-of-the-art solutions. The proposed Xbar layout demarcates from the prevalent photonic schemes that rely on the implementation of intended matrices factorized via the Singular Value Decomposition (SVD); instead, it harnesses the power of interference within a novel design where each matrix element can be mapped by one-to-one correspondence to a single, designated Xbar node, bringing down the number of programming steps to only one. In this paper, we present the theoretical foundations of the Xbar, proving that its insertion losses do not scale with the node losses as opposed to the exponential scaling witnessed by the SVD based counterparts. This leads to a matrix design with significantly lower overall insertion losses and improved scalability potential compared to SVD-based schemes, allowing for the employment of alternative node technologies with lower energy consumption and higher operational speed credentials. Finally, we theoretically validate that the proposed Xbar architecture is the first linear operator that supports fidelity restoration, outperforming SVD schemes in loss- and phase-error fidelity performance.

We demonstrate a programmable analog opto-electronic (OE) circuit that can be configured to provide a range of nonlinear activation functions for incoherent neuromorphic photonic circuits at up to 10 Gbaud line-rates. We present a set of well-known activation functions that are typically used to train DL models including tanh-, sigmoid-, ReLU- and inverted ReLU-like activations, introducing also a series of novel photonic nonlinear functions that are referred to as Rectified Sine Squared (ReSin), Sine Squared with Exponential tail (ExpSin) and Double Sine Squared. Experimental validation for all these activation functions is performed at 10 Gbaud operation. The ability of the mathematically modelled photonic activation functions to train Deep Neural Networks (DNNs) has been verified through their employment in Deep Learning (DL) models for MNIST and CIFAR10 classification purposes, comparing their performance against corresponding NNs that utilize an ideal ReLU activation function.

During the last decade, deep neural networks (DNNs) have become increasingly important for the resolution of numerous practical problems.¹ With the amount of computing power required to train such DNNs doubling every 3.5 months,² academic and industrial researchers started gravitating toward new technologies and hardware accelerators to keep pace with this growth. Highly parallelized computing solutions, including graphic processing units (GPUs),³ field programmable gate arrays,⁴ tensor processing units (TPUs),⁵ and application-specific integrated circuits,^{6 – 8} have been developed to accelerate the matrix-vector multiplication (MVM) operations, which form the most time- and power-consuming computational task in DNNs.⁹