Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to redefine and refine their role based on the progress in both research fields. We present the current set of critical challenges faced by the computing industry and provide a thorough review of photonic Network-on-Chip (pNoC) architectures and experimental demonstrations, concluding to the main obstacles that still impede the materialization of these concepts. We propose the employment of optics in chip-to-chip (C2C) computing architectures rather than on-chip layouts toward reaping their benefits while avoiding technology limitations on the way to manycore set-ups. We identify multisocket boards as the most prominent application area and present recent advances in optically enabled multisocket boards, revealing successful 40 Gb/s transceiver and routing capabilities via integrated photonics. These results indicate the potential to bring energy consumption down by more than 60% compared to current QuickPath Interconnect (QPI) protocol, while turning multisocket architectures into a single-hop low-latency setup for even more than four interconnected sockets, which form currently the electronic baseline. We go one step further and demonstrate how optically-enabled eight-socket boards can be combined via a 256 × 256 Hipoλaos Optical Packet Switch into a powerful 256-node disaggregated system with less than 335 ns latency, forming a highly promising solution for the latency-critical rack-scale memory disaggregation era. Finally, we discuss the perspective for disintegrated computing via optical technologies as a mean to increase the number of synergized high-performance cores overcoming die area constraints, introducing also the concept of cache disintegration via the use of future off-die ultrafast optical cache memory chiplets.

The relentless growth of Artificial Intelligence (AI) workloads has fueled the drive towards non-Von Neuman architectures and custom computing hardware. Neuromorphic photonic engines aspire to synergize the low-power and high-bandwidth credentials of light-based deployments with novel architectures, towards surpassing the computing performance of their electronic counterparts. In this paper, we review recent progress in integrated photonic neuromorphic architectures and analyze the architectural and photonic hardware-based factors that limit their performance. Subsequently, we present our approach towards transforming silicon coherent neuromorphic layouts into high-speed and high-accuracy Deep Learning (DL) engines by combining robust architectures with hardware-aware DL training. Circuit robustness is ensured through a crossbar layout that circumvents insertion loss and fidelity constraints of state-of-the-art linear optical designs. Concurrently, we employ DL training models adapted to the underlying photonic hardware, incorporating noise- and bandwidth-limitations together with the supported activation function directly into Neural Network (NN) training. We validate experimentally the high-speed and high-accuracy advantages of hardware-aware DL models when combined with robust architectures through a SiPho prototype implementing a single column of a 4:4 photonic crossbar. This was utilized as the pen-ultimate hidden layer of a NN, revealing up to 5.93% accuracy improvement at 5GMAC/sec/axon when noise-aware training is enforced and allowing accuracies of 99.15% and 79.8% for the MNIST and CIFAR-10 classification tasks. Channel-aware training was then demonstrated by integrating the frequency response of the photonic hardware in NN training, with its experimental validation with the MNIST dataset revealing an accuracy increase of 12.93% at a record-high rate of 25GMAC/sec/axon.

We demonstrate a novel interferometric coherent photonic crossbar architecture (Xbar) that can realize any tensor operator and allows for total loss-induced fidelity restoration, offering at the same time significant dimension scalability credentials compared to respective state-of-the-art solutions. The proposed Xbar layout demarcates from the prevalent photonic schemes that rely on the implementation of intended matrices factorized via the Singular Value Decomposition (SVD); instead, it harnesses the power of interference within a novel design where each matrix element can be mapped by one-to-one correspondence to a single, designated Xbar node, bringing down the number of programming steps to only one. In this paper, we present the theoretical foundations of the Xbar, proving that its insertion losses do not scale with the node losses as opposed to the exponential scaling witnessed by the SVD based counterparts. This leads to a matrix design with significantly lower overall insertion losses and improved scalability potential compared to SVD-based schemes, allowing for the employment of alternative node technologies with lower energy consumption and higher operational speed credentials. Finally, we theoretically validate that the proposed Xbar architecture is the first linear operator that supports fidelity restoration, outperforming SVD schemes in loss- and phase-error fidelity performance.

We demonstrate a programmable analog opto-electronic (OE) circuit that can be configured to provide a range of nonlinear activation functions for incoherent neuromorphic photonic circuits at up to 10 Gbaud line-rates. We present a set of well-known activation functions that are typically used to train DL models including tanh-, sigmoid-, ReLU- and inverted ReLU-like activations, introducing also a series of novel photonic nonlinear functions that are referred to as Rectified Sine Squared (ReSin), Sine Squared with Exponential tail (ExpSin) and Double Sine Squared. Experimental validation for all these activation functions is performed at 10 Gbaud operation. The ability of the mathematically modelled photonic activation functions to train Deep Neural Networks (DNNs) has been verified through their employment in Deep Learning (DL) models for MNIST and CIFAR10 classification purposes, comparing their performance against corresponding NNs that utilize an ideal ReLU activation function.

Recently there has been growing interest in using photonics to perform the linear algebra operations of neuromorphic and quantum computing applications, aiming at harnessing silicon photonics’ (SiPho) high-speed and energy-efficiency credentials. Accurately mapping, however, a matrix into optics remains challenging, since state-of-the-art optical architectures are sensitive to fabrication imperfections. This leads to reduced fidelity that degrades as the insertion losses of the optical matrix nodes or the matrix dimensions increase. In this work, we present the experimental deployment of a 4 × 4 coherent crossbar (Xbar) as a silicon chip and validate experimentally its theoretically predicted fidelity restoration credentials. We demonstrate the experimental implementation of 10,000 arbitrary linear transformations achieving a record-high fidelity of 99.997% ± 0.002, limited mainly by the measurement equipment. Our work represents an integrated optical circuit providing almost unity and loss-independent fidelity in the realization of arbitrary matrices, highlighting light’s credentials in resolving complex computations.