We present results of our investigations on nickel silicidation of top-down fabricated silicon nanowires (SiNWs). Control over the silicidation process is important for the application of SiNWs in reconfigurable field-effect transistors. Silicidation is performed using a rapid thermal annealing process on the SiNWs fabricated by electron beam lithography and inductively-coupled plasma etching. The effects of variations in crystallographic orientations of SiNWs and different NW designs on the silicidation process are studied. Scanning electron microscopy and transmission electron microscopy are performed to study Ni diffusion, silicide phases, and silicide–silicon interfaces. Control over the silicide phase is achieved together with atomically sharp silicide–silicon interfaces. We find that {111} interfaces are predominantly formed, which are energetically most favorable according to density functional theory calculations. However, control over the silicide length remains a challenge.

The mid-infrared localized surface plasmon resonances are realized in hyperdoped Si and can be spectrally tuned by fabricating nano-antenna arrays. Our results are promising for the integration of plasmonic sensors into the on-chip CMOS platform.

The transport properties of novel device architectures depend strongly on the morphology and the quality of the interface between contact and channel materials. In silicon nanowires with nickel silicide contacts, NiSi${}_2$ –Si interfaces are particularly important as NiSi${}_2$ is often found as the phase adjacent to the silicide–silicon interface during and after the silicidation. The interface orientation of these NiSi${}_2$ –Si interfaces as well as the ability to create abrupt and flat interfaces, ultimately with atomic sharpness, is essential for the properties of diverse emerging device concepts. We present a combined experimental and theoretical study on NiSi${}_2$ –Si interfaces. Interfaces in silicon nanowires were fabricated using silicidation and characterized by high-resolution (scanning) transmission electron microscopy. It is found that {111} interfaces occur in ⟨110⟩ nanowires. A tilted interface and an arrow-shaped interface are observed, which depends on the nanowire diameter. We have further modeled NiSi${}_2$ –Si interfaces by density functional theory. Different crystallographic orientations and interface variations, e.g., due to interface reconstruction, are compared with respect to interface energy densities. The {111} interface is energetically most favorable, which explains the experimental observations. Possible ways to control the interface type are discussed.

Top-down fabrication of reconfigurable field effect transistors (RFET) is a prerequisite for large-scale integration. Silicon (Si) nanowire-based RFET devices have been extensively studied in the past decade. To achieve superior RFET performance, it is necessary to develop scalable devices with controlled silicidation of the channels, a high on-off ratio, and symmetrical p- and n- on-currents. In this work, we present the electrical performance of scalable RFET devices based on Si nanowires featuring controlled silicide lengths attained through millisecond-range flash lamp annealing (FLA). The electronic properties of the transistors are optimized by tuning the different gate schemes and gate dielectric materials for nanowire passivation. We explore gate capacitive control on the energy bands in the conduction of charge carriers using various dielectric materials. The transfer characteristics of a single top-gated device with SiO₂ as gate dielectric show enhanced ambipolar behavior with negligible hysteresis, low subthreshold swing values of 210 mV/dec, and an on-off ratio (I _ON/I _OFF) of up to ∼10⁸ (8 orders of magnitude). The devices also demonstrate excellent electron and hole symmetry values with a record pn on-current symmetry of 1.03. Utilizing high-performance, scalable RFET devices with elevated symmetrical on-currents holds great promise for reducing delay and power consumption in future energy-efficient integrated circuitry.

This work demonstrates the novel concept of a mixed-dimensional reconfigurable field effect transistor (RFET) by combining a one-dimensional (1D) channel material such as a silicon (Si) nanowire with a two-dimensional (2D) material as a gate dielectric. An RFET is an innovative device that can be dynamically programmed to perform as either an n- or p-FET by applying appropriate gate potentials. In this work, an insulating 2D material, hexagonal boron nitride (hBN), is introduced as a gate dielectric and encapsulation layer around the nanowire in place of a thermally grown or atomic-layer-deposited oxide. hBN flake was mechanically exfoliated and transferred onto a silicon nanowire-based RFET device using the dry viscoelastic stamping transfer technique. The thickness of the hBN flakes was investigated by atomic force microscopy and transmission electron microscopy. The ambipolar transfer characteristics of the Si-hBN RFETs with different gating architectures showed a significant improvement in the device's electrical parameters due to the encapsulation and passivation of the nanowire with the hBN flake. Both n- and p-type characteristics measured through the top gate exhibited a reduction of hysteresis by 10-20 V and an increase in the on-off ratio (I_ON/I_OFF) by 1 order of magnitude (up to 10⁸) compared to the values measured for unpassivated nanowire. Specifically, the hBN encapsulation provided improved electrostatic top gate coupling, which is reflected in the enhanced subthreshold swing values of the devices. For a single nanowire, an improvement up to 0.97 and 0.5 V/dec in the n- and p-conduction, respectively, is observed. Due to their dynamic switching and polarity control, RFETs boast great potential in reducing the device count, lowering power consumption, and playing a crucial role in advanced electronic circuitry. The concept of mixed-dimensional RFET could further strengthen its functionality, opening up new pathways for future electronics.