This paper presents the research on tactile sensing system on chip. The tactile sensing chips comprise of 5 × 5 array of Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) devices and temperature sensors. The POSFET devices are obtained by spin coating piezoelectric polymer, poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)), films directly on to the gate area of Metal Oxide Semiconductor (MOS) transistors. The tactile sensing chips are able to measure dynamic contact forces and temperatures. The readout and the data acquisition system to acquire the tactile signals are also presented. The chips have been extensively tested over wide range of dynamic contact forces and temperatures and the experimental results are presented. The paper also reports the research on tactile sensing chips with POSFET array and the integrated electronics.

Tunnel field effect transistors (TFETs) have emerged as one of the most promising post-CMOS transistor technologies. In this paper, we: 1) review the perspectives of such devices for low-power high-frequency analog integrated circuit applications (e.g., GHz operation with sub-0.1 mW power consumption); 2) discuss and employ a compact TFET device model in the context of the g _m /I _d integrated analog circuit design methodology; and 3) compare several proposed TFET technologies for such applications. The advantages of TFETs arise since these devices can operate in the sub-threshold region with larger transconductance-to-current ratio than traditional FETs, which is due to the current turn-on mechanism being interband tunneling rather than thermionic emission. Starting from technology computer-aided design and/or analytical models for Si-FinFETs, graphene nano-ribbon (GNR) TFETs and InAs/GaSb TFETs at the 15-nm gate-length node, as well as InAs double-gate TFETs at the 20-nm gate-length node, we conclude that GNR TFETs might promise larger bandwidths at low-voltage drives due to their high current densities in the sub-threshold region. Based on this analysis and on theoretically predicted properties, GNR TFETs are identified as one of the most attractive field effect transistor technologies proposed-to-date for ultra-low power analog applications.

Wireless sensor networks (WSNs) simulation is essential for the development and optimization of such kind of networks. In this paper we present modifications made to prowler, a WSNs simulator, making its MAC protocol model compliant with the crossbow MICAz mote running on Tiny OS. Moreover, we added radio propagation models to the simulator and, most important, we implemented an energy consumption estimation model of the CC2420 radio chip. Then, the simulator is addressed to the development of WSNs applications with a particular emphasis on energy consumption optimization (and consequently battery lifetime). We present as case study the comparison between simulated results of two different physical deployments, showing how real operating conditions can affect and modify the system behavior in comparison with the results predicted by theoretical analysis.

Wireless sensor node (WSN) lifetime is correlated with the battery current usage profile. State of the art in wireless sensor nodes current consumption shows that available models have not been extensively tested and experimentally validated. This work aims to seek answers to the following questions: is it accurate the node lifetime prediction obtained with available models? Moreover, is the radio transceiver always responsible for depleting the battery? In order to perform experimental evaluations, we implemented a prototype board that enables to visualize charge extracted from batteries and battery current consumption waveforms of wireless sensor nodes. We selected benchmarks that represent usual tasks in WSN applications and we made experimental evaluations of battery current consumption. Finally, a battery full-depletion time measurement has been performed. Overall results are presented and discussed.

In this paper we show that tunnel field effect transistors (TFETs) biased in the subthreshold region promise several advantages for low-power/high-frequency analog IC applications (e.g. GHz operation with sub-0.1 mW power consumption). Analytical and TCAD models for graphene nano-ribbon (GNR) and InAs/GaSb nanowire TFETs are employed, respectively, for the first time in subthreshold analog circuit examples using the g _m /I _d integrated circuit (IC) design technique. From comparison of these TFET technologies with traditional FETs it is observed that due to the higher currents per unit gate width at low voltage for TFETs, smaller, higher speed, and lower power analog circuits are enabled.

A memristor is an electrical element, which has been conjectured in 1971 to complete the lumped circuit theory. Currently, researchers use memristor emulators through diodes, inductors, and other passive (or active) elements to study circuits with possible attractors, chaos, and ways of implementing nonlinear transformations for low-voltage novel computing paradigms. However, to date, such passive memristor emulators have been voltage-controlled. In this study, a novel circuit realization of a passive current-controlled passive inductorless emulator is established. It overcomes the lack of passive current-controlled memristor commercial devices, and it can be used as part of more sophisticated circuits. Moreover, it covers a gap in the state of the art because, currently, only passive circuit voltage-controlled memristor emulators and active current-controlled emulators have been developed and used. The emulator only uses two diodes, two resistors, and one capacitance and is passive. The formal theory and simulations validate the proposed circuit, and experimental measurements were performed. The parameter conditions of numerical simulations and experiments are consistent. Simulations were performed with an input current amplitude of and frequencies of up to and measurements were carried out with an input current amplitude of and frequency of in order to compare with the state of the art.