In this paper, we propose a cost-efficient beamforming optimization algorithm for multi-user wireless communication systems associated with the intelligent reflecting surface (IRS). From the baseline successive refinement algorithm, which gives a sub-optimal solution for the power minimization problem under the signal-to-interference-plus-noise-ratio (SINR) constraint at each user, several optimization techniques are proposed to reduce the computation complexity while maintaining the algorithm-level performance. To reduce the number of required multiply-accumulate (MAC) operations, we first simplify the complicated matrix inversion by utilizing the channel hardening effect. We also present the two-phase refinement process for the group-level optimization of phase-shift elements, further relaxing the computation complexity as well as the processing latency. Applying the proposed optimization techniques, as a result, numerical results show that the fully-optimized algorithm can reduce the computational costs by up to 89.4% while showing less than 1 dB power loss, leading to the practical solution for the next-generation IRS-aided communication.

In massive multiple-input multiple-output (MIMO) systems using a large number of antennas, it would be difficult to connect high-resolution analog-to-digital converters (ADCs) to each antenna component due to high cost and energy consumption problems. To resolve these issues, there has been much work on implementing symbol detectors and channel estimators using low-resolution ADCs for massive MIMO systems. Although it is intuitively true that using low-resolution ADCs makes it possible to save a large amount of energy consumption in massive MIMO systems, the relationship between energy consumption using low-resolution ADCs and detection performance has not been properly analyzed yet. In this paper, the tradeoff between different detectors and total baseband energy consumption including flexible ADCs is thoroughly analyzed taking the optimal fixed-point operations performed during the detection processes into account. In order to minimize the energy consumption for the given channel condition, the proposed scheme selects the best mode among various processing options while supporting the target frame error rate. The numerous case studies reveal that the proposed work remarkably saves the energy consumption of the massive MIMO processing compared with the existing schemes.

In order to effectively reduce buffer energy consumption, which constitutes a significant part of the total energy consumption in a convolutional neural network (CNN), it is useful to apply different amounts of energy conservation effort to the different levels of a CNN as the buffer energy to total energy usage ratios can differ quite substantially across the layers of a CNN. This paper proposes layerwise buffer voltage scaling as an effective technique for reducing buffer access energy. Error-resilience analysis, including inter-layer effects, conducted during design-time is used to determine the specific buffer supply voltage to be used for each layer of a CNN. Then these layer-specific buffer supply voltages are used in the CNN for image classification inference. Error injection experiments with three different types of CNN architectures show that, with this technique, the buffer access energy and overall system energy can be reduced by up to 68.41% and 33.68%, respectively, without sacrificing image classification accuracy.

The number of devices served by baseband stations is constantly increasing due to the rising data traffic in modern communication systems. In order to support large-scale multi-user multiple-input multiple-output (MU-MIMO) systems and achieve their capacity, it is necessary to consider power allocation and user selection along with precoding. This paper introduces a scalable MU-MIMO precoding processor that solves the joint optimization problem for precoding, power allocation, and user selection. We define custom vector instructions and dedicate vector arithmetic operators based on the RV32IM instruction set architecture to efficiently support various MU-MIMO baseband processing scenarios. The proposed vector operators include parallel dual-precision multipliers to enable energy-efficient processing by adjusting the computing resolution of each step without degrading the algorithm-level quality. The proposed processor is fabricated using 28nm CMOS technology and is capable of solving the state-of-the-art joint optimization problem in only 0.51ms for the $64\times 64$ large-scale MU-MIMO configuration. Our processor achieves up to 17.4 times higher processing efficiency compared to previous precoder design, even when supporting the largest number of users and the most complicated algorithm.

This paper presents a novel sparsity-aware CNN accelerator supporting the edge-level image recognition even for noisy images. In the proposed accelerator, we characterize the class of input noises by utilizing the FFT-based on-the-fly noise classifier. The proposed convolution engine then accesses the external memory to load the dedicated network that provides the accurate inference processing for the detected noise class. To save the energy consumed by the external DRAM accesses, in addition, we present the filter-level pruning algorithm with the memory-reduced indexing scheme, which can reduces the processing latency by utilizing the indexing method. To verify the effectiveness of the proposed methods, the proposed CNN accelerator is implemented in the commercialized FPGA-based platform, achieving the processing rate of 57.6GOPS at the speed of 100MHz. Utilizing the dedicated network for each noise type, the prototype accelerator reduces the energy consumption by 62% compared to the conventional network with a similar recognition accuracy, which is suitable for the intelligent edge-level devices subjected to the various noises in practice.