Stateful logic enables highly energy‐efficient computation because the time and energy consumption for data transfer between the memory and the processing units in the traditional computation system can significantly be saved due to the combined functionalities of logic operation and nonvolatile memory. The logic primitive circuit, usually composed of resistive switching memory or memristor units, is the fundamental and kernel element to build a stateful logic family. However, the current stateful logic primitive circuits cannot be configured between the devices from the adjacent layers of the 3D crossbar array (CBA) which largely limited its application in high‐density and capacity memory arrays. Herein, a new stateful logic primitive circuit is presented based on the structure of two antiparallel bipolar memristors. The presented logic primitive circuit enables a complete set of stateful logic operation and is compatible with a 3D CBA. The working principle and validity of the logic design were experimentally demonstrated by either a real TiO₂‐based memristive circuit or the HSPICE simulation. Furthermore, a space‐time‐wise cascading method was demonstrated by XOR and the full adder functions based on a CBA, and its merits were further elucidated through comparison with different logic families with various cascading methods.

Resistive switching random access memory (RRAM) shows its potential to be a promising candidate as the basic in-memory computing unit for deep neural networks (DNN) accelerator design due to its non-volatile, low power, and small footprint properties. The RRAM based crossbar array (RRAM CBA) is usually employed to accelerate DNN because of its intrinsic characteristic of executing multiplication-and-accumulation (MAC) operation according to Kirchhoffs’ law. However, some major non-ideal effects including IR-drop and Stuck-at-Faults (SAF) in real RRAM CBA are typically ignored in the DNN accelerator design because of the considerations of training speed and design closure. Such non-ideal effects will conduct the variations of output column current and voltage and further cause serious degradation in computing accuracy. Thus, direct mapping from the weights of DNN model without considering the IR-drop and SAF to RRAM CBA is unrealistic. In this work, two efficient and optimized methods including adding additional tunable RRAM row and Trans-impedance amplifier (TIA) based RRAM are proposed to recover the computation accuracy with a view to reducing variation of the output column current of the RRAM CBA and output voltage of the TIA in each column respectively. The two optimized methods are evaluated in different sizes of RRAM CBA and different resistance levels of RRAM cell. The simulation results show that the two optimized methods can further suppress the degradation of computing accuracy induced by IR-drop and SAF for LeNet-5 with the MNIST dataset and VGG16 with the CIFAR-10 dataset.

This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting the cascaded integrator feed-forward (CIFF) structure, the proposed architecture employs unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function. Since to the lossless residue extraction and summation, it exhibits high efficiency in realizing the strong noise-shaping (NS) effect. Fabricated in a 65-nm 1P9M CMOS technology, the prototype NS-SAR ADC consumes $113.02~\mu \text{W}$ when operating at a 1.2-V supply voltage and at a sampling rate of 20 MS/s. It achieves a peak Schreier FoM of 176.73 dB with a signal to noise and distortion-ratio (SNDR) of 79.3 dB at an oversampling ratio (OSR) of 16.