Recent papers have pointed out the interest to study convergence in the presence of multiple equilibrium points (EPs) (multistability) for neural networks (NNs) with nonsymmetric cooperative (nonnegative) interconnections and neuron activations modeled by piecewise linear (PL) functions. One basic difficulty is that the semiflows generated by such NNs are monotone but, due to the horizontal segments in the PL functions, are not eventually strongly monotone (ESM). This notwithstanding, it has been shown that there are subclasses of irreducible interconnection matrices for which the semiflows, although they are not ESM, enjoy convergence properties similar to those of ESM semiflows. The results obtained so far concern the case of cooperative NNs without delays. The goal of this paper is to extend some of the existing results to the relevant case of NNs with delays. More specifically, this paper considers a class of NNs with PL neuron activations, concentrated delays, and a nonsymmetric cooperative interconnection matrix A and delay interconnection matrix A ^τ . The main result is that when A + A ^τ satisfies a full interconnection condition, then the generated semiflows, which are monotone but not ESM, satisfy a limit set dichotomy analogous to that valid for ESM semiflows. It follows that there is an open and dense set of initial conditions, in the state space of continuous functions on a compact interval, for which the solutions converge toward an EP. The result holds in the general case where the NNs possess multiple EPs, i.e., is a result on multistability, and is valid for any constant value of the delays.

Positive feedback source-coupled logic (PFSCL) is proposed as an alternative logic style to traditional SCL logic, which is often used in high-resolution mixed-signal integrated circuits. Positive feedback allows for significantly reducing the NMOS transistors' aspect ratio compared to traditional single-ended SCL gates for equal values of design constraints. The resulting reduction in NMOS parasitic capacitances permits a significant speed up, which can be traded off to achieve a power saving for a given speed constraint, as well as a silicon area reduction. PFSCL gates are analytically modeled in terms of their static parameters and delay, which are expressed as a function of bias current, transistors' aspect ratios and process parameters. Spectre simulations by using a 0.35-/spl mu/m CMOS process confirm that the proposed models are sufficiently accurate in practical cases. PFSCL gates are also compared with traditional SCL circuits by resorting to two different metrics: the gate delay in a Ring Oscillator and that of an inverter with a fan-out of 4. The comparison confirms that PFSCL logic is faster than SCL logic in most cases, and design conditions leading to a speed advantage are identified. As a result, PFSCL gates are an interesting alternative to traditional SCL circuits in mixed-signal applications requiring a high speed or a good balance with power dissipation.

This paper considers a class of nonsmooth neural networks with discontinuous hard-limiter (signum) neuron activations for solving time-dependent (TD) systems of algebraic linear equations (ALEs). The networks are defined by the subdifferential with respect to the state variables of an energy function given by the L₁ norm of the error between the state and the TD-ALE solution. It is shown that when the penalty parameter exceeds a quantitatively estimated threshold the networks are able to reach in finite time, and exactly track thereafter, the target solution of the TD-ALE. Furthermore, this paper discusses the tightness of the estimated threshold and also points out key differences in the role played by this threshold with respect to networks for solving time-invariant ALEs. It is also shown that these convergence results are robust with respect to small perturbations of the neuron interconnection matrices. The dynamics of the proposed networks are rigorously studied by using tools from nonsmooth analysis, the concept of subdifferential of convex functions, and that of solutions in the sense of Filippov of dynamical systems with discontinuous nonlinearities.

In this paper, positive feedback source-coupled logic (PFSCL) gates are analyzed from a design point of view. The design space is explored through analytical relationships which relate the gate delay, power consumption and noise margin, which are modeled through a simplified circuit analysis. To be more specific, a simple and accurate model of the noise margin is used to derive a systematic design strategy to size the transistors' aspect ratios ensuring an assigned noise margin for a given bias current. From the knowledge of the transistor sizes, the gate delay is then expressed as a function of the bias current and the supply voltage, both of which define the static power consumption of PFSCL gates, as well as of the logic swing, which determines the noise margin. Therefore, this delay model simply relates the speed performance, the power consumption and the noise margin of PFSCL gates, and accounts for the dependence on the fan-in and fan-out. Extensive SPICE simulations with a 0.18-m CMOS process confirm the adequate accuracy of the analytical models and the validity of the approximations introduced to simplify the analysis, and a practical design example of an equality comparator is also presented. In order to derive clear guidelines to manage the delay-power-noise margin tradeoff, PFSCL gates are analyzed in typical design cases (i.e., design for high speed, low power and power efficiency). For the sake of completeness, the effect of each design parameter on the silicon area occupied by a PFSCL gate is also qualitatively analyzed. The resulting criteria are thus useful to design PFSCL gates without resorting to time-consuming design iterations with a trial and error approach based on simulations.