A 9-bit 80 MS/s successive approximation register analog-to-digital converter (ADC), which is suitable for low power and a small area, is presented. The 9-bit capacitor array consists of only 16 unit capacitors and a coupling capacitor due to the proposed binary-weighted split-capacitor arrays with a merged-capacitor switching technique. The proposed ADC includes a comparator with offset cancellation and uses digital calibration for error correction. The ADC is implemented in a 65-nm complimentary metal-oxide-semiconductor technology and occupies an active area of 0.068 mm² with a reference buffer. The differential and integral nonlinearities of the ADC are less than 0.37 and 0.40 LSB, respectively. The ADC shows a signal-to-noise-distortion ratio of 50.71 dB, a spurious-free dynamic range of 66.72 dB, and an effective number of bits of 8.13 bits with a 78 MHz sinusoidal input at 80 MS/s. The ADC consumes 3.4 mW with the reference buffer at a 1.0-V supply and achieves a figure of merit of 78 fJ/conversion step.

This paper describes the fabrication and characterization of a reconfigurable Yagi-Uda antenna based on a silicon reflector with a solid-state plasma. The silicon reflector, composed of serially connected p-i-n diodes, forms a highly dense solid-state plasma by injecting electrons and holes into the intrinsic region. When this plasma silicon reflector is turned on, the front-realized gain of the antenna increases by more than 2 dBi beyond 5.3 GHz. To achieve the large gain increment, the structure of the antenna is carefully designed with the aid of semiconductor device simulation and antenna simulation. By using an aluminum nitride (AlN) substrate with high thermal conductivity, self-heating effects from the high forward current in the p-i-n diode are efficiently suppressed. By comparing the antenna simulation data and the measurement data, we estimated the conductivity of the plasma silicon reflector in the on-state to be between 10⁴ and 10⁵ S/m. With these figures, silicon material with its technology is an attractive tunable material for a reconfigurable antenna, which has attracted substantial interest from many areas, such as internet of things (IoT) applications, wireless network security, cognitive radio, and mobile and satellite communications as well as from multiple-input-multiple-output (MIMO) systems.

This brief presents a class-C voltage-controlled oscillator (VCO) that ensures a robust start-up with low phase noise and high power efficiency. The proposed start-up scheme, which uses a voltage converter that operates according to the output state, relieves the start-up difficulty by supplying a time-varying bias voltage to the core transistors and allows the VCO to operate in an optimal state. The start-up circuitry is enabled only during initial operation, so power efficiency is improved without phase noise degradation. Furthermore, a capacitor array with a high quality factor is implemented by a direct capacitor connection that exhibits low series resistance. Fabricated with a 65-nm CMOS, the VCO demonstrates a frequency tuning range of 13.1% from 19.3 to 22.0 GHz. The measured minimum phase noise at a 1-MHz offset is −106.33 dBc/Hz at an oscillation frequency of 19.7 GHz, while dissipating 3.8-mW of power from a 1.0-V supply. The VCO occupies an active area of 0.064 mm ² . It reveals a figure-of-merit and figure-of-merit with area of −186.4 and −198.3 dBc/Hz, respectively.

This paper presents a substrate-integrated waveguide (SIW)-fed magneto-electric dipole antenna comprising an inclined bridge-connected radiator based on aluminum posts for millimeter-wave broadband applications. The proposed structure creates additional resonant frequencies for the electric and magnetic dipoles by bridging the two metal posts and adjusting their inclination angles, thereby improving the impedance bandwidth. Additionally, it also improves the flatness of the gain while maintaining the maximum realized gain. The impedance bandwidth of S11<–10 dB in the single element is 36.2% with a maximum gain of 9.1 dBi, and the 3 dB gain bandwidth exceeds 40%. Furthermore, an efficient pattern-based matching technique is developed in the array design to mitigate the effect of the bonding film that combines two different SIW layers. The proposed 8 × 8 array antenna demonstrates a measured impedance bandwidth of 25.2% from 33.6 GHz to 43.3 GHz with a maximum gain of 26.2 dBi at 42.5 GHz.

This brief presents a time-division switching (TDS) technique aimed at excess loop delay (ELD) compensation for a continuous-time sigma-delta modulator (SDM) based on a thirdorder single op-amp resonator (SOR). By reconfiguring the transfer function of the SOR with the clock signal, the proposed method achieves ELD compensation, resulting in improved power and area efficiency, as well as enhanced immunity to nonidealities. The proposed SDM is implemented using a single amplifier to realize a third-order resonator, and it employs a single feedback digital-to-analog converter using the proposed TDS ELD compensation method. The modulator, which occupies only 0.094 mm of the active area, was fabricated in a 180-nm CMOS technology. It consumes 100-μW power from a 1.8-V supply, and it achieves a peak signal-to-noise and distortion ratio of 63.8 dB and a dynamic range of 65.2 dB in a 400-kHz signal bandwidth when clocked at 40 MHz. The proposed method offers a simple and attractive solution for ELD compensation in thirdorder SOR-based SDMs.

A second‐order loop filter (LF) that uses a single op‐amp resonator is presented for continuous‐time delta–sigma modulators. The proposed technique improves the power and area efficiency of the LF and enhances the controllability of the transfer function and the resonating condition by providing a new RC network. A second‐order modulator has been designed to confirm the effectiveness of the proposed scheme. Implemented in a 130 nm CMOS, the prototype modulator occupies an active area of 0.098 mm ² and consumes 5.23 mW power from a 1.2 V supply. It achieves a peak SNDR of 60.95 dB over a 15 MHz signal bandwidth with a sampling frequency of 780 MHz.