This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18-μm standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of 10.2 μA. It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of 0.22 μs is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of 0.1 μs.

This article presents a high power supply rejection ratio (PSRR) low dropout (LDO) regulator with a low quiescent current. A low quiescent current capacitive feed-forward ripple cancellation (CFFRC) technique is proposed to cancel the power supply noise. With this technique, low power consumption is achieved via feed-forward capacitors and back-to-back pseudo-resistors bias. This design was fabricated using the 0.18- $\mu \text{m}$ CMOS technology. The entire proposed LDO consumes a quiescent current of 0.9 $\mu \text{A}$ . Compared with an LDO without enhancement, at the maximum load current of 200 mA, the measured PSRR has an enhancement of −22 dB at 1 MHz.

This paper presents a class-AB operational transconductance amplifier (OTA) with a high slew rate. The proposed class-AB OTA is applied with a slew-rate enhancement technique using an extremely low quiescent current. The additional current-reference common-mode feedback loop resolves the susceptibility to process, voltage, and temperature fluctuations resulting from slew-rate enhancement transistors. The proposed class-AB OTA is most widely used in block design, including, a switched-capacitor circuit, analog-to-digital converter, digital-to-analog converter, low-dropout regulator, and switched-capacitor DC-DC converters. In this study, performance was validated by applying the proposed class-AB OTA to a switched-capacitor delta-sigma modulator which requires high performance and high precision. The circuit was designed and simulated using a 0.18-μm complementary metal-oxide semiconductor process.

This brief presents a low-dropout regulator (LDO) for power-efficient Internet of Things (IoT) devices. When IoT devices are in low-power standby mode, the proposed LDO senses the load current and enters an ultra-low-power mode to enable an extremely low-power system. The proposed LDO alternates between two modes of operation. One is the ultra-low-power mode in which the core circuit of the LDO is turned off to save power, and the other is an active mode in which all circuit components are on. The successful operation of the proposed scheme is demonstrated by implementing and measuring silicon LDO chips, resulting in an extremely low-quiescent current of 13.5 nA and a superior figure-of-merit (FOM).

This paper proposes a 300 mA low-dropout (LDO) regulator using an IQ of only 0.94 μA, which has the advantage of minimizing power consumption in the standby mode of a battery-based system. The LDO uses a source follower buffer with dynamic biasing to maintain loop stability and load transient response performance. Under light-load conditions, the buffer enters a fully-off state because there is a sub-nA bias current. Therefore, the LDO uses a dual output operational transconductance amplifier (DO-OTA) for operation under light-load conditions. The second output of the DO-OTA for light-load operation in the LDO forms an additional feedback path instead of the fully-off buffer. The second output of the DO-OTA is designed to consume a current lower than the bias current of the buffer while operating. Furthermore, the buffer in the LDO is designed for operation above 5 mA IL. While the buffer is operating, the dynamic biasing current of the buffer is used as the second output of the DO-OTA. The second output of the DO-OTA has lower output impedance characteristics than its main output, so the LDO can secure loop stability under light-load conditions by lowering the DC gain. As a result, the LDO exhibits load transient response performance up to 300 mA by using a minimal IQ under the no-load condition. The LDO is based on a 180 nm bipolar-CMOS-DMOS (BCDMOS) process and covers an area of approximately 256 × 143 μm2. The measured IQ is 0.94 μA under the no-load condition with a maximum load current of 300 mA.