In this paper, we present a novel approach that aims to solve one of the main challenges in hand gesture recognition tasks in static images, to compensate for the accuracy lost when trained models are used to interpret completely unseen data. The model presented here consists of two main data-processing stages. A deep neural network (DNN) for performing handshape segmentation and classification is used in which multiple architectures and input image sizes were tested and compared to derive the best model in terms of accuracy and processing time. For the experiments presented in this work, the DNN models were trained with 24,000 images of 24 signs from the American Sign Language alphabet and fine-tuned with 5200 images of 26 generated signs. The system was real-time tested with a community of 10 persons, yielding a mean average precision and processing rate of 81.74% and 61.35 frames-per-second, respectively. As a second data-processing stage, a bidirectional long short-term memory neural network was implemented and analyzed for adding spelling correction capability to our system, which scored a training accuracy of 98.07% with a dictionary of 370 words, thus, increasing the robustness in completely unseen data, as shown in our experiments.

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

In this correspondence, a method is presented for estimating double-selective channels using superimposed training (ST). The estimator is based on a subspace projection of the time-varying channel onto a set of two dimensional orthogonal functions. These functions are formed via the outer product of the discrete prolate spheroidal basis vectors and the universal basis vectors. This approach allows the channel to be expanded in both the time-delay and time dimensions with the fewest parameters when incomplete channel statistics are given. This correspondence also provides a theoretical performance analysis of the estimation algorithm and its corroboration via simulations. It is shown that this new method provides an enhancement in channel estimation when compared with state-of-the-art approaches.

This paper introduces the design of a filtenna for cognitive radio systems. Four varactor diodes, which are inserted in the bandpass filter, are used to achieve the desired tunability. The proposed bandpass filter is integrated with a wideband monopole antenna. The bandpass filter is achieved by using two coupled defected ground structure (DGS) resonators and two coupled microstrip lines ended with two stubs. The monopole antenna is designed to operate in a frequency band from 1.3 GHz to 3 GHz. The four varactor diodes are used to tune the antenna resonance frequency from 2.7 GHz to 2 GHz when the capacitance increases from 1.55 pF to 2.67 pF. The performance of the proposed filtenna is validated by simulation and measurements from a fabricated prototype. Finally, the proposed filtenna is tested using the Software Defined Radio (SDR) platform bladeRF. This transceiver can transmit and receive in a wide frequency range of 0.3 GHz up to 3.8 GHz, which makes it suitable for testing the proposed reconfigurable filtenna.

The increasing use of smaller technologies in the manufacture of analog front-ends (AFEs) for communication systems has increased the impact their non-ideal components produce. This results in a significant degradation of the system performance that must be identified and addressed. In particular, the I/Q imbalance is commonly estimated and compensated via digital signal processing techniques using training sequences. In order to preclude the rise of other non-idealities, such as the non-linearity of the power amplifier (PA), these training sequences should be chosen to have a low peak-to-average power ratio (PAPR). In addition, it is desirable that these techniques have reduced computational complexity for minimizing estimation times and area resources. This paper presents a novel I/Q imbalance estimation algorithm that is computationally simple, it only requires adders and shifters, while exhibiting a PAPR ≤ 2. It can include the transmitter and receiver I/Q imbalances as well as the multipath phenomena. It is based on a newly used property of Golay complementary sequences (GCS). The statistical efficiency and low complexity of the proposed algorithm are proved, while its flexibility is illustrated under several extreme test cases.