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He received the degree of M.S. and D.S. in Electronics and Telecommunications at the Center for Scientific Research and Higher Education of Ensenada B.C. (CICESE) in 2005 and 2016, respectively. Since 2018 he has been a full-time professor at the Academic Unit of Electrical Engineering of the Autonomous University of Zacatecas and a collaborator of the CIDTE. His research lines include wireless communications, Software Defined Radio, signal processing for communications, RF on Chip networks, cooperative networks and MIMO.
Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.
Jose Gomez-Rodriguez; Remberto Sandoval-Arechiga; Salvador Ibarra-Delgado; Viktor Rodriguez-Abdala; Jose Vazquez-Avila; Ramon Parra-Michel. A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities. Micromachines 2021, 12, 183 .
AMA StyleJose Gomez-Rodriguez, Remberto Sandoval-Arechiga, Salvador Ibarra-Delgado, Viktor Rodriguez-Abdala, Jose Vazquez-Avila, Ramon Parra-Michel. A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities. Micromachines. 2021; 12 (2):183.
Chicago/Turabian StyleJose Gomez-Rodriguez; Remberto Sandoval-Arechiga; Salvador Ibarra-Delgado; Viktor Rodriguez-Abdala; Jose Vazquez-Avila; Ramon Parra-Michel. 2021. "A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities." Micromachines 12, no. 2: 183.