Constant input and output mismatch circles in the output load plane are introduced as the basis for low-noise amplifier design methodology. Optimum tradeoff between input and output matching levels results as the application of a design chart providing, at the same time, the corresponding stage transducer gain. The role of degenerative series feedback is studied and systematically embedded in the design procedure, thus providing a direct way to evaluate its optimum level.

Radioastronomy applications, as well as others, require ultra-low-noise front ends for high-sensitivity receivers. In this way, the image produced from a radio-telescope using such advanced components has a higher resolution and therefore allows scientists to obtain a clearer representation of the environment. The low-noise amplifier is the key component of a high sensitivity receiver (demonstrating a very low noise figure, even in the millimeter-wave frequency region). Such electrical performance is obtained from the combined use of an advanced technology (f_T and f_max > 250 GHz, L_G <; 0, 1 μm) and appropriate design methodologies that take into account electrical specifications and system constraints in the context of the targeted application. In this contribution, we will present both the performance of the employed technology (OMMIC 70 nm GaAs mHEMT) and the related low-noise design methodologies that have led to the realization of four different LNAs operating from 5 GHz up to 100 GHz and beyond.

The design, fabrication and test of a 2-18 GHz monolithic Low Noise Amplifier utilizing 0.25 μm AlGaN/GaN HEMT technology is reported. The measured noise figure of the amplifier is less than 4.7 dB over the 2 - 18 GHz frequency range, exhibiting a minimum of 3.3 dB at 3 GHz. The LNA gain is 23 dB. Even being a low-noise amplifier, the MMIC can withstand 10W input CW RF power, demonstrating no apparent degradation: to the authors knowledge this is the best RF LNA survivability reported to date in this frequency range using GaN technology.

Design and performance of a gallium nitride (GaN)-on-Si mixer for the Ka-band satellite telecom applications are presented in this letter. GaN-on-Si offers the advantage of high-volume production even for millimeter-wave applications. A single-balanced architecture is selected as an optimum tradeoff between circuit complexity and rejection of local oscillator (LO) harmonics. An alternative circuit topology is adopted where the in-phase combiner and hybrid quadrature couplers, used to obtain the desired signal phasing at mixer output, are also employed as circuit elements to inject external bias voltages so to optimize the mixer's conversions loss (CL). The mixer features 11-dB CL, 11- and 22-dBm P1dB and IIP3 respectively, in the 26-31-GHz bandwidth when driven by a 10-dBm LO level. Monolithic microwave integrated circuit area is less than 6 mm².

The design, realization, and test of a $Ka$ -band gallium nitride (GaN) monolithic microwave-integrated circuit (MMIC) single-chip front-end (SCFE) is presented. The MMIC, realized in OMMIC’s 100-and 60-nm gate length GaN on Silicon process, integrates high-power and low-noise amplification together with transmit or receive selection switches in a 4.7 $\times$ 3.0 mm chip area. The SCFE is conceived for active electronically scanned antenna applications operating from 32 to 36 GHz. In RX mode, a typical noise figure of 3.2 dB and gain better than 3B have been measured. In TX mode, the typical output power and the power-added efficiency (PAE) are 35 dBm and 16%, respectively. A drain bias point trade-off analysis is performed so the power amplifier’s transistors channel temperature remains below 160 $^{\circ}$ while design charts are provided for the synthesis of the low-noise amplifier (LNA) block. Finally, 100-and 60-nm gate length transistors are combined on the MMIC to improve its performance in terms of receive noise figure and transmit gain and output power. To the best of the authors’ knowledge, this GaN SCFE features the highest operating frequency reported in the open literature regarding integrated GaN/Si solutions and compares well with GaN/SiC MMICs especially considering the CW test condition here reported while concurrently fulfilling the FET’s channel temperature requirement.

Source degenerative feedback is extensively applied in the low-noise amplifier design. The beneficial effects of this technique are well established in the open literature. However, the designer is often left to trial-and-error or optimization procedures to identify the adequate amount of feedback when other linear requirements, such as signal matching, come into play. This issue is even more relevant in multistage designs. In this article, we present a synthesis procedure and the relevant design chart to identify the optimum feedback inductor value on all transistors of an N-stage amplifier to obtain a perfect match at its external ports in conjunction with amplifier noise figure minimization and a specified gain requirement. It is shown that the method is applicable to arbitrary N values although it becomes more elaborate for N greater than 6. The method is deterministic as opposed to optimization or trial-and-error-based procedures. The design flow is illustrated at first through a four-stage design with ideal matching elements and subsequently validated by an monolithic microwave integrated circuit (MMIC) test vehicle designed and realized in the WIN foundry's Gallium Arsenide PIH1-10 process. The measured performance of the test vehicle is NF = 1.9 dB, 26 dB gain, typical I/O return loss of 15 dB in the 26.5-29.5-GHz bandwidth, and practically ideal behavior at the design frequency of 28 GHz.