The design, realization, and test of a $Ka$ -band gallium nitride (GaN) monolithic microwave-integrated circuit (MMIC) single-chip front-end (SCFE) is presented. The MMIC, realized in OMMIC’s 100-and 60-nm gate length GaN on Silicon process, integrates high-power and low-noise amplification together with transmit or receive selection switches in a 4.7 $\times$ 3.0 mm chip area. The SCFE is conceived for active electronically scanned antenna applications operating from 32 to 36 GHz. In RX mode, a typical noise figure of 3.2 dB and gain better than 3B have been measured. In TX mode, the typical output power and the power-added efficiency (PAE) are 35 dBm and 16%, respectively. A drain bias point trade-off analysis is performed so the power amplifier’s transistors channel temperature remains below 160 $^{\circ}$ while design charts are provided for the synthesis of the low-noise amplifier (LNA) block. Finally, 100-and 60-nm gate length transistors are combined on the MMIC to improve its performance in terms of receive noise figure and transmit gain and output power. To the best of the authors’ knowledge, this GaN SCFE features the highest operating frequency reported in the open literature regarding integrated GaN/Si solutions and compares well with GaN/SiC MMICs especially considering the CW test condition here reported while concurrently fulfilling the FET’s channel temperature requirement.

Source degenerative feedback is extensively applied in the low-noise amplifier design. The beneficial effects of this technique are well established in the open literature. However, the designer is often left to trial-and-error or optimization procedures to identify the adequate amount of feedback when other linear requirements, such as signal matching, come into play. This issue is even more relevant in multistage designs. In this article, we present a synthesis procedure and the relevant design chart to identify the optimum feedback inductor value on all transistors of an N-stage amplifier to obtain a perfect match at its external ports in conjunction with amplifier noise figure minimization and a specified gain requirement. It is shown that the method is applicable to arbitrary N values although it becomes more elaborate for N greater than 6. The method is deterministic as opposed to optimization or trial-and-error-based procedures. The design flow is illustrated at first through a four-stage design with ideal matching elements and subsequently validated by an monolithic microwave integrated circuit (MMIC) test vehicle designed and realized in the WIN foundry's Gallium Arsenide PIH1-10 process. The measured performance of the test vehicle is NF = 1.9 dB, 26 dB gain, typical I/O return loss of 15 dB in the 26.5-29.5-GHz bandwidth, and practically ideal behavior at the design frequency of 28 GHz.

In this paper a GaN-on-Si MMIC Low-Noise Amplifier (LNA) working in the Ka-band is shown. The chosen technology for the design is a 100 nm gate length HEMT provided by OMMIC foundry. Both small-signal and noise models had been previously extracted by the means of an extensive measurement campaign, and were then employed in the design of the presented LNA. The amplifier presents an average noise figure of 2.4 dB, a 30 dB average gain value, and input/output matching higher than 10 dB in the whole 34–37.5 Ghz design band, while non-linear measurements testify a minimum output 1 dB compression point of 23 dBm in the specific 35–36.5 GHz target band. This shows the suitability of the chosen technology for low-noise applications.

A Ka -band low-noise amplifier for low-consumption robust receivers is presented in this letter. The monolithic microwave integrated circuit (MMIC) is designed on a 100 nm GaN-on-Si technology provided by OMMIC foundry and decibel gain, average noise figure (NF) of 1.5 dB, with input–output return losses better than 15 dB in the whole 27–31 GHz design band. Large signal measurements show a OP _{1 dBcp} of +16 dBm and survivability to RF input power verified up to +25 dBm without showing critical degradation. These performances have been achieved with only 150 mW dc power consumption in linear operating condition, 30% less than other Ka -band GaN LNAs published in the open literature.

Motivated by the growing interest towards low-cost, restriction-free MMIC processes suitable for multi-function, possibly space-qualified applications, this contribution reports the extraction of reliable linear models for two advanced GaN-on-Si HEMT technologies, namely OMMIC’s D01GH (100 nm gate length) and D006GH (60 nm gate length). This objective is pursued by means of both classical and more novel approaches. In particular, the latter include a nondestructive method for determining the extrinsic resistances and an optimizaion-based approach to extracting the remaining parasitic elements: these support standard DC and RF measurements in order to obtain a scalable, bias-dependent equivalent-circuit model capturing the small-signal behavior of the two processes. As to the noise model, this is extracted by applying the well known noise-temperature approach to noise figure measurements performed in two different frequency ranges: a lower band, where a standard Y-factor test bench is used, and an upper band, where a custom cold-source test bench is set up and described in great detail. At 5 V drain-source voltage, minimum noise figures as low as 1.5 dB and 1.1 dB at 40 GHz have been extracted for the considered 100 nm and 60 nm HEMTs, respectively: this testifies the maturity of both processes and the effectiveness of the gate length reduction. The characterization and modeling campaign, here presented for the first time, has been repeatedly validated by published designs, a couple of which are reviewed for the Reader’s convenience.