Entangled carbon nanofibers (CNFs) were synthesized on a flexible carbon fabric (CF) via water-assisted chemical vapor deposition at 800°C at atmospheric pressure utilizing iron (Fe) nanoparticles as catalysts, ethylene (C₂H₄) as the precursor gas, and argon (Ar) and hydrogen (H₂) as the carrier gases. Scanning electron microscopy, transmission electron microscopy, and electron dispersive spectroscopy were employed to characterize the morphology and structure of the CNFs. It has been found that the catalyst (Fe) thickness affected the morphology of the CNFs on the CF, resulting in different capacitive behaviors of the CNF/CF electrodes. Two different Fe thicknesses (5 and 10 nm) were studied. The capacitance behaviors of the CNF/CF electrodes were evaluated by cyclic voltammetry measurements. The highest specific capacitance, approximately 140 F g⁻¹, has been obtained in the electrode grown with the 5-nm thickness of Fe. Samples with both Fe thicknesses showed good cycling performance over 2,000 cycles.

Data center energy usage keeps growing every year and will continue to increase with rising demand for ecommerce, scientific research, social networking, and use of streaming video services. The miniaturization of microelectronic devices and an increasing demand for clock speed result in high heat flux systems. By adopting direct liquid cooling, the high heat flux and high power demands can be met, while the reliability of the electronic devices is greatly improved. Cold plates which are mounted directly on to the chips facilitate a lower thermal resistance path originating from the chip to the incoming coolant. An attempt was made in the current study to characterize a commercially available cold plate which uses warm water in carrying the heat away from the chip. A mock package mimicking a processor chip with an effective heat transfer area of 6.45 cm2 was developed for this study using a copper block heater arrangement. The thermo-hydraulic performance of the cold plates was investigated by conducting experiments at varying chip power, coolant flow rates, and coolant temperature. The pressure drop (ΔP) and the temperature rise (ΔT) across the cold plates were measured, and the results were presented as flow resistance and thermal resistance curves. A maximum heat flux of 31 W/cm2 was dissipated at a flow rate of 13 cm3/s. A resistance network model was used to calculate an effective heat transfer coefficient by revealing different elements contributing to the total resistance. The study extended to different coolant temperatures ranging from 25 °C to 45 °C addresses the effect of coolant viscosity on the overall performance of the cold plate, and the results were presented as coefficient of performance (COP) curves. A numerical model developed using 6SigmaET was validated against the experimental findings for the flow and thermal performance with minimal percentage difference.

Thermoelectric (TE) modules utilize available temperature differences to generate electricity by the Seebeck effect. The current study investigates the merits of employing thermoelectrics to harvest additional electric energy instead of just cooling concentrating photovoltaic (CPV) modules by heat sinks (heat extractors). One of the attractive options to convert solar energy into electricity efficiently is to laminate TE modules between CPV modules and heat extractors to form a CPV-TE/thermal (CPV-TE/T) hybrid system. In order to perform an accurate estimation of the additional electrical energy harvested, a coupled-field model is developed to calculate the electrical performance of TE devices, which incorporates a rigorous interfacial energy balance including the Seebeck effect, the Peltier effect, and Joule heating, and results in better predictions of the conversion capability. Moreover, a 3D multiphysics computational model for the HCPV-TE/T water collector system consisting of a solar concentrator, 10 serially connected GaAs/Ge photovoltaic (PV) cells, 300 couples of bismuth telluride TE modules, and a cooling channel with heat-recovery capability, is implemented by using the commercial FE–tool Comsol Multiphysics^®. A conjugate heat transfer model is used, assuming laminar flow through the cooling channel. The performance and efficiencies of the hybrid system are analyzed. As compared with the traditional photovoltaic/thermal (PV/T) system, a comparable thermal efficiency and a higher 8% increase of the electrical efficiency can be observed through the PV-TE hybrid system. Additionally, with the identical convective surface area and cooling flow rate in both configurations, the PV-TE/T hybrid system yields higher PV cell temperatures but more uniform temperature distributions across the cell array, which thus eliminates the current matching problem; however, the higher cell temperatures lower the PV module's fatigue life, which has become one of the biggest challenges in the PV-TE hybrid system.

In raised floor data centers, tiles with high open area ratio or complex understructure are used to fulfill the demand of today's high-density computing. Using more open tiles reduces the pressure drop across the raised floor with the potential advantages of increased airflow and lower noise. However, it introduces the disadvantage of increased nonuniformity of airflow distribution. In addition, there are various tile designs available on the market with different opening shapes or understructures. Furthermore, a physical separation of cold and hot aisles (containment) has been introduced to minimize the mixing of cold and hot air. In this study, three types of floor tiles with different open area, opening geometry, and understructure are considered. Experimentally validated detail models of tiles were implemented in computational fluid dynamics (CFD) simulations to address the impact of tile design on the cooling of information technology (IT) equipment in both open and enclosed aisle configurations. Also, impacts of under-cabinet leakage on the IT equipment inlet temperature in the provisioned and under-provisioned scenarios are studied. In addition, a predictive equation for the critical under-provisioning point that can lead to a no-flow condition in IT equipment with weaker airflow systems is presented. Finally, the impact of tile design on thermal performance in a partially enclosed aisle with entrance doors is studied and discussed.

In this paper, the impact of direct liquid cooling (DLC) system failure on the information technology (IT) equipment is studied experimentally. The main factors that are anticipated to affect the IT equipment response during failure are the central processing unit (CPU) utilization, coolant set point temperature (SPT), and the server type. These factors are varied experimentally and the IT equipment response is studied in terms of chip temperature and power, CPU utilization, and total server power. It was found that failure of this cooling system is hazardous and can lead to data center shutdown in less than a minute. Additionally, the CPU frequency throttling mechanism was found to be vital to understand the change in chip temperature, power, and utilization. Other mechanisms associated with high temperatures were also observed such as the leakage power and the fans' speed change. Finally, possible remedies are proposed to reduce the probability and the consequences of the cooling system failure.

Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, and memory controller has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly nonuniform power distribution results in a large temperature gradient with localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can affect performance by a factor as much as 30%. In this paper, a multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. The analysis was performed for 90 nm Pentium IV Northwood architecture operating at 3 GHz clock speed. Each functional unit on the die has a specific role, so functional units with similar roles were grouped together. Thus, the actual Pentium IV die was divided into four groups (front end, execution cores, bus and L2, and out-of-order engine). Repositioning constraints were determined using circuit delay models of major functional units in a micro-architectural simulator. Thus, depending on the scenario, relocating functional units can result in virtually no performance loss (less than 2% is assumed to be minimal and is reported as 0%) to as much as 30% performance loss. From the results, the minimum and the maximum temperatures were $56.6°C$ and $62.2°C$. This $ΔT$ corresponds to thermal design power of 60.2 W. For microprocessors with higher thermal design power (115 W) and operating at higher clock speed, higher $ΔT$ can be realized. Based on this paper’s analysis, the optimized scenario resulted in a junction temperature of $56.6°C$ at the cost of a 14% performance loss.