Jitter is one of the crucial factors used to characterize high-speed serial links and integrated circuit performance. Jitter decomposition is key tool with which to characterize jitter at a given bit error rate (BER). In this article, a novel jitter decomposition algorithm is proposed using convolutional neural networks to decompose random jitter (RJ) and deterministic jitter (DJ) by images of a jitter histogram, and predict the total jitter (TJ) at a BER of 10−12. The jitter histogram – that is, training data – is obtained by modeling the high-speed serial link in an advanced design system. The test results verify the feasibility and accuracy of the proposed method. The RJ mean absolute error (MAE) of the test is 0.8721 ps and the error rate 6.74%, and the DJ MAE is 4.8684 ps and the error rate 2.03%, and TJ MAE is 8.9406 ps and the average error rate 2.13%. In addition, results show that the effectiveness of the proposed method is better than most other jitter decomposition methods by evaluating the average error rate.

A novel method of jitter decomposition by 1 Dimension-convolutional neural network (1D-CNN) using jitter histogram points is proposed for decomposing in the time interval error (TIE) of oscilloscope. Unlike the traditional jitter decomposition method based on the dual-Dirac model and gaussian mixture model (GMM), the proposed jitter decomposition can reduce complexity and improve accuracy. The proposed method consists of a four-layer 1D-convolutional layer and multi-layer perceptron (MLP). Experimental results show that the proposed approach can decompose the total jitter (TJ) into deterministic jitter (DJ) and random jitter (RJ) and is better than the traditional jitter decomposition method, i.e., GMM, Fast Fourier transform and time lag correlation (FFT+TLC). Besides, results show that the proposed method’s performance is better than 2D-PointCNN, PointRNN, CNN, and PointANN.

Jitter is one of the main factors affecting the bit error rate, and jitter decomposition is a crucial tool with which to characterize jitter at a given BER. In this article, we address this problem based on PointNet and propose a PointNet-based dual-Dirac model (PointNet-DD), where its input is the two-dimensional point cloud formed by the coordinate of the jitter histogram. In particular, we develop a feature extractor, where the stride size of the one-dimensional convolution layer of PointNet is changed to better learn the local features, the corresponding variance and mean features hidden under the jitter histogram point cloud are extracted by global max pooling and global average pooling, respectively. Then, we introduce a dual-Dirac model in the network for jitter calculation to make the estimated deterministic jitter and random jitter more accurate. Consequently, the PointNet-DD can improve the mean absolute error of jitter decomposition. Finally, this approach is practically tested on the test circuits. Experimental results show that the performance, robustness, space, and time of the proposed method are better than other methods.

Jitter is becoming an important factor in high-speed serial link and integrated circuits (ICs). Generating controllable jitter plays a crucial role in simulating the test environment of high-data links, evaluating the performance of IC, preventing jitter in high-speed serial link, and even testing the synchronous trigger circuit. In this paper, a digital synthesis for jitter generation and a logical combination method for selecting jitter on the rising edge or falling edge of a data pattern are presented. Precisely controllable jitter is generated by digital synthesis, including sinusoidal period jitter, rectangular period jitter, duty cycle distortion (DCD) jitter, and adjustable random jitter. Additionally, the validity and accuracy of the proposed method were demonstrated by hardware experiments, where the jitter frequency had an accuracy of ±30 ppm and the jitter amplitude had a step of 2 ps.