Jitter is one of the crucial factors used to characterize high-speed serial links and integrated circuit performance. Jitter decomposition is key tool with which to characterize jitter at a given bit error rate (BER). In this article, a novel jitter decomposition algorithm is proposed using convolutional neural networks to decompose random jitter (RJ) and deterministic jitter (DJ) by images of a jitter histogram, and predict the total jitter (TJ) at a BER of 10−12. The jitter histogram – that is, training data – is obtained by modeling the high-speed serial link in an advanced design system. The test results verify the feasibility and accuracy of the proposed method. The RJ mean absolute error (MAE) of the test is 0.8721 ps and the error rate 6.74%, and the DJ MAE is 4.8684 ps and the error rate 2.03%, and TJ MAE is 8.9406 ps and the average error rate 2.13%. In addition, results show that the effectiveness of the proposed method is better than most other jitter decomposition methods by evaluating the average error rate.

In this paper, a novel ultra-narrow pulse generation approach is proposed. It is based on the decomposition and synthesis of pulse edges. Through controlling their relative delay, an ultra-narrow pulse could be generated. By employing field programmable gate array digital synthesis technology, the implemented pulse generator is with programmable ability. The amplitude of pulse signals is controlled by the radio frequency amplifiers and bias tees, and high precision can be achieved. More importantly, the proposed approach can break through the limitation of device’s propagation delay and optimize the resolution and the accuracy of the pulse width significantly. The implemented pulse generator has two channels, whose minimum pulse width, frequency range, and amplitude range are 100 ps, 15 MHz–1.5 GHz, and 0.1 Vpp–1.8 Vpp, respectively. Both resolution of pulse width and channel delay are 1 ps, and amplitude resolution is 10 mVpp.

A novel method of jitter decomposition by 1 Dimension-convolutional neural network (1D-CNN) using jitter histogram points is proposed for decomposing in the time interval error (TIE) of oscilloscope. Unlike the traditional jitter decomposition method based on the dual-Dirac model and gaussian mixture model (GMM), the proposed jitter decomposition can reduce complexity and improve accuracy. The proposed method consists of a four-layer 1D-convolutional layer and multi-layer perceptron (MLP). Experimental results show that the proposed approach can decompose the total jitter (TJ) into deterministic jitter (DJ) and random jitter (RJ) and is better than the traditional jitter decomposition method, i.e., GMM, Fast Fourier transform and time lag correlation (FFT+TLC). Besides, results show that the proposed method’s performance is better than 2D-PointCNN, PointRNN, CNN, and PointANN.

Jitter is one of the main factors affecting the bit error rate, and jitter decomposition is a crucial tool with which to characterize jitter at a given BER. In this article, we address this problem based on PointNet and propose a PointNet-based dual-Dirac model (PointNet-DD), where its input is the two-dimensional point cloud formed by the coordinate of the jitter histogram. In particular, we develop a feature extractor, where the stride size of the one-dimensional convolution layer of PointNet is changed to better learn the local features, the corresponding variance and mean features hidden under the jitter histogram point cloud are extracted by global max pooling and global average pooling, respectively. Then, we introduce a dual-Dirac model in the network for jitter calculation to make the estimated deterministic jitter and random jitter more accurate. Consequently, the PointNet-DD can improve the mean absolute error of jitter decomposition. Finally, this approach is practically tested on the test circuits. Experimental results show that the performance, robustness, space, and time of the proposed method are better than other methods.

This paper proposes a new high-resolution digital-to-time converter architecture based on a field programmable gate array and digital-to-analog converter (DAC). A real-time algorithm of time–-amplitude mapping is proposed, which converts the vertical resolution of the DAC to the timing resolution and realizes the ultra-high resolution timing signal generation. Moreover, the relationship between the timing resolution and the vertical resolution and the sampling rate of DAC is discussed. Based on this, arbitrarily distributed random timing signals and editable timing signal sequence functions are realized. This method is verified in the experiment on Xilinx XCKU040 and Texas Instrument DAC37J82. Furthermore, a timing resolution of 1 ps is realized. A time range of 4.2 ns to 999 s, an editable sequence length of 1–128k, and excellent nonlinear performance are achieved. In addition, functions for arbitrarily distributed random timing signals and signal bursts are tested. This method can be flexibly deployed on existing hardware and satisfy almost all test requirements.

In the design of SDRAM-based arbitrary waveform generators, the conflict between the randomness of dynamic memory output data flow and the requirement of seamless signal output is a non-negligible problem, especially in generators with hopping functions and high sampling rates. By imposing appropriate constraints in the design, the continuity of the output signal and the high throughput utilization can be guaranteed, and the constraints can be modeled to obtain the design boundary requirements under different specifications. In this paper, we analyze the throughput model of SDRAM and the access characteristics of an arbitrary waveform generator with jump capability. We establish a minimum waveform segment length model and a buffer size model to guarantee continuous signal output, which can obtain sufficient conditions for seamless synthesis of arbitrary waveform generators and be used to support the repeat/jump function of multi-segment waveforms. Experimental results on a DDR3 SDRAM-based generator show that the minimum waveform segment length obtained is within 11 words of the measured boundary, and the minimum buffer size is within 10 words of the measured boundary, which can effectively improve hardware resource utilization.