In this research, the hafnium titanate oxide thin films, Ti_xHf_1–xO₂, with titanium contents of x = 0, 0.25, 0.9, and 1 were deposited on germanium substrates by atomic layer deposition (ALD) at 300 °C. The approximate deposition rates of 0.2 Å and 0.17 Å per cycle were obtained for titanium oxide and hafnium oxide, respectively. X-ray Photoelectron Spectroscopy (XPS) indicates the formation of GeO_x and germanate at the interface. X-ray diffraction (XRD) indicates that all the thin films remain amorphous for this deposition condition. The surface roughness was analyzed using an atomic force microscope (AFM) for each sample. The electrical characterization shows very low hysteresis between ramp up and ramp down of the Capacitance-Voltage (CV) and the curves are indicative of low trap densities. A relatively large leakage current is observed and the lowest leakage current among the four samples is about 1 mA/cm² at a bias of 0.5 V for a Ti_0.9Hf_0.1O₂ sample. The large leakage current is partially attributed to the deterioration of the interface between Ge and Ti_xHf_1–xO₂ caused by the oxidation source from HfO₂. Consideration of the energy band diagrams for the different materials systems also provides a possible explanation for the observed leakage current behavior.

The 4 at. % zirconium-doped zinc oxide (ZnO:Zr) films grown by atomic layer deposition (ALD) were annealed at various temperatures ranging from 350 to 950 °C. The structural, electrical, and optical properties of rapid thermal annealing (RTA) treated ZnO:Zr films have been evaluated to find out the stability limit. It was found that the grain size increased at 350 °C and decreased between 350 and 850 °C, while creeping up again at 850 °C. UV–vis characterization shows that the optical band gap shifts towards larger wavelengths. The Hall measurement shows that the resistivity almost keeps constant at low annealing temperatures, and increases rapidly after treatment at 750 °C due to the effect of both the carrier concentration and the Hall mobility. The best annealing temperature is found in the range of 350–550 °C. The ZnO:Zr film-coated glass substrates show good optical and electrical performance up to 550 °C during superstrate thin film solar cell deposition.

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future.

A powerful characterization technique, pulse capacitance-voltage (CV) technique, was used to investigate oxide traps before and after annealing for lanthanide zirconium oxide thin films deposited on n-type Si (111) substrates at 300 °C by liquid injection Atomic Layer Deposition (ALD). The results indicated that: (1) more traps were observed compared to the conventional capacitance-voltage characterization method in LaZrO_x; (2) the time-dependent trapping/de-trapping was influenced by the edge time, width and peak-to-peak voltage of a gate voltage pulse. Post deposition annealing was performed at 700 °C, 800 °C and 900 °C in N₂ ambient for 15 s to the samples with 200 ALD cycles. The effect of the high temperature annealing on oxide traps and leakage current were subsequently explored. It showed that more traps were generated after annealing with the trap density increasing from 1.41 × 10¹² cm⁻² for as-deposited sample to 4.55 × 10¹² cm⁻² for the 800 °C annealed one. In addition, the leakage current density increase from about 10⁻⁶ A/cm² at V_g = +0.5 V for the as-deposited sample to 10⁻³ A/cm² at V_g = +0.5 V for the 900 °C annealed one.

Anomalous capacitance-voltage (CV) behavior was observed in MOS devices with zirconium oxide gate dielectrics using pulse CV technique. The relative positions of up and down CV traces measured by pulse technique were opposite to those by conventional CV measurement. This unusual phenomenon cannot be inconsistently explained by charge trapping and de-trapping mechanisms. Therefore, a hypothesis related with interface dipoles was proposed. With regard to the formation of the interface dipole, it may be related to the oxygen density difference between the high-k layer and native SiO_x layer. In addition, this anomaly was sensitive to growth temperature as well as post-metal-annealing process. However, after annealing in either nitrogen or forming gas ambient, the relative positions of up and down CV curves measured by the pulse technique were consistent with those obtained by conventional CV measurement.