In an increasingly data-rich world the need for developing computing systems that cannot only process, but ideally also interpret big data is becoming continuously more pressing. Brain-inspired concepts have shown great promise towards addressing this need. Here we demonstrate unsupervised learning in a probabilistic neural network that utilizes metal-oxide memristive devices as multi-state synapses. Our approach can be exploited for processing unlabelled data and can adapt to time-varying clusters that underlie incoming data by supporting the capability of reversible unsupervised learning. The potential of this work is showcased through the demonstration of successful learning in the presence of corrupted input data and probabilistic neurons, thus paving the way towards robust big-data processors.

Emerging brain-inspired architectures call for devices that can emulate the functionality of biological synapses in order to implement new efficient computational schemes able to solve ill-posed problems. Various devices and solutions are still under investigation and, in this respect, a challenge is opened to the researchers in the field. Indeed, the optimal candidate is a device able to reproduce the complete functionality of a synapse, i.e. the typical synaptic process underlying learning in biological systems (activity-dependent synaptic plasticity). This implies a device able to change its resistance (synaptic strength, or weight) upon proper electrical stimuli (synaptic activity) and showing several stable resistive states throughout its dynamic range (analog behavior). Moreover, it should be able to perform spike timing dependent plasticity (STDP), an associative homosynaptic plasticity learning rule based on the delay time between the two firing neurons the synapse is connected to. This rule is a fundamental learning protocol in state-of-art networks, because it allows unsupervised learning. Notwithstanding this fact, STDP-based unsupervised learning has been proposed several times mainly for binary synapses rather than multilevel synapses composed of many binary memristors. This paper proposes an HfO2-based analog memristor as a synaptic element which performs STDP within a small spiking neuromorphic network operating unsupervised learning for character recognition. The trained network is able to recognize five characters even in case incomplete or noisy characters are displayed and it is robust to a device-to-device variability of up to +/-30%.

Advanced brain-chip interfaces with numerous recording sites bear great potential for investigation of neuroprosthetic applications. The bottleneck towards achieving an efficient bio-electronic link is the real-time processing of neuronal signals, which imposes excessive requirements on bandwidth, energy and computation capacity. Here we present a unique concept where the intrinsic properties of memristive devices are exploited to compress information on neural spikes in real-time. We demonstrate that the inherent voltage thresholds of metal-oxide memristors can be used for discriminating recorded spiking events from background activity and without resorting to computationally heavy off-line processing. We prove that information on spike amplitude and frequency can be transduced and stored in single devices as non-volatile resistive state transitions. Finally, we show that a memristive device array allows for efficient data compression of signals recorded by a multi-electrode array, demonstrating the technology’s potential for building scalable, yet energy-efficient on-node processors for brain-chip interfaces.

Neuromorphic architectures offer great promise for achieving computation capacities beyond conventional Von Neumann machines. The essential elements for achieving this vision are highly scalable synaptic mimics that do not undermine biological fidelity. Here we demonstrate that single solid-state TiO₂memristors can exhibit non-associative plasticity phenomena observed in biological synapses, supported by their metastable memory state transition properties. We show that, contrary to conventional uses of solid-state memory, the existence of rate-limiting volatility is a key feature for capturing short-term synaptic dynamics. We also show how the temporal dynamics of our prototypes can be exploited to implement spatio-temporal computation, demonstrating the memristors full potential for building biophysically realistic neural processing systems.

The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic yet computationally efficient device models. Here, we present a ReRAM model where device current-voltage characteristics and resistive switching rate are expressed as a function of a) bias voltage and b) initial resistive state. The model versatility is validated on detailed characterization data, for both filamentary valence change memory and non-filamentary ReRAM technologies, where device resistance is swept across its operating range using multiple input voltage levels. Furthermore, the proposed model embodies a window function which features a simple mathematical form analytically describing resistive state response under constant bias voltage as extracted from physical device response data. Its Verilog-A implementation captures the ReRAM memory effect without requiring integration of the model state variable, making it suitable for fast and/or large-scale simulations and overall inter-operable with current design tools.

Selectorless crossbar arrays of resistive randomaccess memory (RRAM), also known as memristors, conduct large sneak currents during operation, which can significantly corrupt the accuracy of cross-point analog resistance (M _t ) measurements. In order to mitigate this issue, we have designed, built, and tested a memristor characterization and testing (mCAT) instrument that forces redistribution of sneak currents within the crossbar array, dramatically increasing M _t measurement accuracy. We calibrated the mCAT using a custom-made 32 × 32 discrete resistive crossbar array, and subsequently demonstrated its functionality on solid-state TiO _2-x RRAM arrays, on wafer and packaged, of the same size. Our platform can measure standalone M _t in the range of 1 kΩ to 1 MΩ with <;1% error. For our custom resistive crossbar, 90% of devices of the same resistance range were measured with <;10% error. The platform's limitations have been quantified using large-scale nonideal crossbar simulations.