Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry^1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm²) devices on unfunctional SiO₂–Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm²) interconnection³ and as a channel of large transistors (roughly 16.5 µm²) (refs. ^4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D–CMOS hybrid microchips for memristive applications—CMOS stands for complementary metal–oxide–semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm². We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

Thermoelectric devices that are flexible and optically transparent hold unique promise for future electronics. However, development of invisible thermoelectric elements is hindered by the lack of p-type transparent thermoelectric materials. Here we present the superior room-temperature thermoelectric performance of p-type transparent copper iodide (CuI) thin films. Large Seebeck coefficients and power factors of the obtained CuI thin films are analysed based on a single-band model. The low-thermal conductivity of the CuI films is attributed to a combined effect of the heavy element iodine and strong phonon scattering. Accordingly, we achieve a large thermoelectric figure of merit of ZT=0.21 at 300 K for the CuI films, which is three orders of magnitude higher compared with state-of-the-art p-type transparent materials. A transparent and flexible CuI-based thermoelectric element is demonstrated. Our findings open a path for multifunctional technologies combing transparent electronics, flexible electronics and thermoelectricity.

Heat transfer processes in micro- and nanoscale devices have become more and more important during the last decades. Scanning thermal microscopy (SThM) is an atomic force microscopy (AFM) based method for analyzing local thermal conductivities of layers with thicknesses in the range of several nm to µm. In this work, we investigate ultrathin films of hexagonal boron nitride (h-BN), copper iodide in zincblende structure (γ-CuI) and some test sample structures fabricated of silicon (Si) and silicon dioxide (SiO₂) using SThM. Specifically, we analyze and discuss the influence of the sample topography, the touching angle between probe tip and sample, and the probe tip temperature on the acquired results. In essence, our findings indicate that SThM measurements include artefacts that are not associated with the thermal properties of the film under investigation. We discuss possible ways of influence, as well as the magnitudes involved. Furthermore, we suggest necessary measuring conditions that make qualitative SThM measurements of ultrathin films of h-BN with thicknesses at or below 23 nm possible.