RRAM is a promising candidate to implement large-capacity in-memory computing on edge AI devices due to its high density. However, the efficiency and accuracy of RRAM-based computing-in-memory (CIM) works are limited by large accumulation currents and device variations. The SRAM-based digital CIM achieves superior performance and efficiency while the adder tree dominates the area. In this paper, a digital RRAM CIM macro is proposed to achieve a better trade-off between accuracy, energy, and performance by three techniques. First, a dynamic voltage sense amplifier is designed to reduce >90% read currents of low resistance state (LRS) cell. Second, an OR gate approximate adder tree is proposed to reduce the area of the adder tree by 40%. Third, a sparse-aware finetuning algorithm is proposed to reduce the accuracy loss of approximate arithmetic to 0.4% on Cifar-10 dataset. The proposed design achieves 1966TOPS/W energy efficiency and 51.2GOPS/Kb normalized throughput at 1-bit precision which is 1.2× and 1.8× higher than previous RRAM-based designs. This work demonstrates the advantage of digital CIM using RRAM devices.

Stroke evaluation is critical for coaches to evaluate players' performance in table tennis matches. However, current methods highly demand proficient knowledge in table tennis and are time-consuming. We collaborate with the Chinese national table tennis team and propose Tac-Valuer, an automatic stroke evaluation framework for analysts in table tennis teams. In particular, to integrate analysts' knowledge into the machine learning model, we employ the latest effective framework named abductive learning, showing promising performance. Based on abductive learning, Tac-Valuer combines the state-of-the-art computer vision algorithms to extract and embed stroke features for evaluation. We evaluate the design choices of the approach and present Tac-Valuer's usability through use cases that analyze the performance of the top table tennis players in world-class events.

This paper proposes an auto loss compensation (ALC) system to attenuate the time-variant path loss for capacitive-coupled body channel communication (CC-BCC). The system employs a time-division gradient indicator to continuously monitor the compensation conditions, and dynamically adjust the compensation inductor through a proportional integral (PI) controller. With the closed-loop topology, the proposed ALC system has two major advantages: first, the path loss induced by the backward coupling effect can be compensated without calibration; second, this system can dynamically attenuate the path loss, even when the channel characteristics vary with time. The simulation and experimental results show that the proposed ALC system can significantly attenuate the backward path loss, especially under wearable and motion scenarios.

Body channel communication (BCC) has the potential to achieve better energy efficiency over other conventional wireless communication schemes, thus becomes a promising solution for the wireless body area network. To deal with the fading and dynamic variation challenges of BCC, the technique of orthogonal frequency-division multiplexing (OFDM) is a promising candidate. However, some basic issues in OFDM including the pilot design and the modulating methods have not been analyzed for BCC. The contribution of this paper includes proposing a dynamic channel model of BCC for system level designing, analyzing the pilot design method, and proposing an adaptive modulating algorithm for BCC. Practical communication experiments based on software define radio are also implemented to validate the the effectiveness of the pilot design method and the modulating algorithm.

Non-volatile computing-in-memory (nvCIM) has become one of the most efficient methods to deal with increasingly complicated neural networks compared to the traditional von Neumann architecture. However, due to the immature fabrication issues, the yield of resistive random access memory (RRAM) cells is limited, which causes the Stuck-At-Faults (SAFs) and decrease of network classification accuracy. In this brief, the bit-aware fault-tolerant hybrid retraining and remapping schemes are proposed to restore the network classification accuracy caused by SAFs. The low weight bits are retrained with the fault mask and the high weight bits are remapped with column swap and zero correction methods. For those bits whose values are still wrong after remapping, the fault index is used to record and calibrate. Experimental results show that the classification accuracy of MNIST, CIFAR-10, and CIFAR-100 is restored from 12.54% to 98.13%, from 10.29% to 90.60%, and from 0.94% to 74.30% with only 10.3% energy consumption and 5.88% area overhead, respectively.

Neural Network (NN) accelerators are widely used in many scenarios, including computer vision, speech recognition, automatic driving, etc. The trained weights of NNs are considered confidential properties due to their commercial value, thus becoming the potential targets for hardware reverse-engineering intruders. In this paper, we propose a low-cost, high-security, easy-to-deploy countermeasure for convolutional neural network (CNN) systolic array against weight reverse-engineering through power side channels. This countermeasure utilizes the clock frequency-switching and phase-shifting techniques to mitigate the power side channels. We further make a design space exploration to trade-off between Side-Channel Analysis (SCA) security and performance by leveraging the non-ideality of CMOS device. The experimental results show that the proposed countermeasure achieves an 81.6% absolute correlation reduction, thus incurring more than 100× power trace consumption (more secure) while maintaining the MAC (multiply-and-accumulate) blocks work at the Pareto-optimal frequencies (Pareto faster).