Gaurav Khanal

Dr. Gaurav Khanal

Laboratory of Microelectronics and VLSI Architectures For DSP, Department of Electronics Engineering, University of Rome “Tor Vergata”, Via Del Politechnico 1, 00133 Rome, Italy
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Research Focus & Metrics

Academic Career Length

10Years (2017-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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7 February 2020 in Electronics
Verified
Journal Article
Open access
PDF file
Gian Carlo Cardarilli Gian Carlo Cardarilli
Gian Carlo Cardarilli
GKGaurav Khanal
Gaurav Khanal
Luca Di NunzioLuca Di Nunzio
Luca Di Nunzio
MRMarco Re
Marco Re
RFRocco Fazzolari
Rocco Fazzolari
RKRaj Kumar
Raj Kumar
An oxygen-rich ZnO-reduced graphene oxide (rGO) thin film was synthesized using a photo-annealing technique from zinc precursor (ZnO)–graphene oxide (GO) sol–gel solution. X-ray diffraction (XRD) results show a clear characteristic peak corresponding to rGO. The scanning electron microscope (SEM) image of the prepared thin film shows an evenly distributed wrinkled surface structure. Transition Metal Oxide (TMO)-based memristive devices are nominees for beyond CMOS Non-Volatile Memory (NVRAM) devices. The two-terminal Metal–TMO (Insulator)–Metal (MIM) memristive device is fabricated using a synthesized ZnO–rGO as an active layer on fluorine-doped tin oxide (FTO)-coated glass substrate. Aluminum (Al) is deposited as a top metal contact on the ZnO–rGO active layer to complete the device. Photo annealing was used to reduce the GO to rGO to make the proposed method suitable for fabricating ZnO–rGO thin-film devices on flexible substrates. The electrical characterization of the Al–ZnO–rGO–FTO device confirms the coexistence of memristive and memimpedance characteristics. The coexistence of memory resistance and memory impedance in the same device could be valuable for developing novel programmable analog filters and self-resonating circuits and systems.

20 November 2024 in Physica Status Solidi (a)
Verified
Journal Article
Open access
AJAyush Jain
Ayush Jain
PSPoonam Subudhi
Poonam Subudhi
GKGaurav Khanal
Gaurav Khanal
Deepak PunethaDeepak Punetha
Deepak Punetha
In this study, a simulation‐based analysis of environmentally friendly, lead‐free perovskite (PVK) solar cells (PSC) with high power conversion efficiency (PCE), is presented. Various PVK materials, including lead‐, tin‐, germanium‐, and tin–germanium‐based compounds, are evaluated through simulations to explore their impact on device performance. Among these, CsSn0.5Ge0.5I3 demonstrates the highest simulated efficiency, with a rectangular cell architecture of 0.45 × 0.9 mm. Key parameters such as thickness, temperature, doping concentration, and bandgap are systematically varied in the simulations to study their effects on device performance. The optimized architecture is found to be Au/Spiro‐MeOTAD (hole‐transport layer)/CsSn0.5Ge0.5I3/TiO2 (electron‐transport layer)/FTO, achieving a simulated PCE of 21.61%, with an open‐circuit voltage (Voc) of 1.2 V, short‐circuit current density (Jsc) of 21.32 mA cm−2, and fill factor of 84.43%. Furthermore, in this study, detailed electrical simulations (electric field distribution, Shockley–Read–Hall recombination, and electron and hole concentrations) and thermal simulations (nonradiative recombination heating, joule heating) of the device are included. In this work, the potential of lead‐free PSCs is underscored and the importance of continuous simulation studies to design eco‐friendly, high‐efficiency photovoltaic devices is highlighted.

4 June 2017
Verified
Book Chapter
Closed access
PDF file
GKGaurav Khanal
Gaurav Khanal
SASimone Acciarito
Simone Acciarito
GCGian Carlo Cardarilli
Gian Carlo Cardarilli
ACAbhishek Chakraborty
Abhishek Chakraborty
Luca Di NunzioLuca Di Nunzio
Luca Di Nunzio
MRMarco Re
Marco Re

29 December 2023 in IEEE Transactions on Nanotechnology
Verified
Journal Article
Closed access
SGSahil Garg
Sahil Garg
BSBhavuk Sharma
Bhavuk Sharma
GKGaurav Khanal
Gaurav Khanal
SKSanjeev Kumar
Sanjeev Kumar
NGNeena Gupta
Neena Gupta
ASAK Singh
AK Singh
This work presents the molybdenum di-sulphide three-phase bridge rectifier integrated circuit utilizing the novel self-switching diode. The self-switching diode has a planar architecture having I- V behavior similar to an ideal diode. The structure of SSD is utilized to design single phase and three phase rectifiers. The performance in terms of rectification efficiency, total harmonic distortion, ripple factor and cut-off frequency has been evaluated and compared for both single and three phase SSDBR. The three-phase self-switching diode bridge rectifier (3P-SSDBR) has a cut-off frequency of ∼400 MHz with minimum total harmonic distortion (THD) and ripple factor (RF) of 4.73% and 0.59, respectively. While, the single phase self-switching diode bridge rectifier (1P-SSDBR) has a cut-off frequency of ∼300 MHz with minimum total harmonic distortion (THD) and ripple factor (RF) of 47.86% and 1.94, respectively. Further, to validate the obtained results, the simulation models have been calibrated with experimental and theoretical findings.