The paper discusses the design process of a full programmable logic controller implemented by means of FPGA device. The PLC is compliant with EN 61131-3 standard. It is equipped with a programmer that allows to transfer a program to the program memory of the controller, and the I/O controller which allows the exchange of information with the outside world, i.e. the signal modules. Some interesting aspects of instruction list and hardware architecture designing are presented, e.g. the PLC structure with a particular emphasis on central processing unit and memory map. The PLC is developed using one FPGA device as a combination of dedicated logic and soft-processor based parts. This gives an opportunity to develop interesting solutions. For example, using dual port RAM gives an opportunity to implement bit/word access without the necessity of masking bits. The paper presents a short description of a designed and written simple integrated development environment.

The article discusses counters defined in the IEC 61131-3 standard. The possible implementations of standard counters function blocks in FPGAs are presented. First, counters are implemented as classical hardware-based modules. Second, counters are designed as the FPGA built-in memory blocks with a single common executing unit. These solutions are compared to each other and compared with counters realized in commercially available PLCs like Siemens SIMATIC S7 controllers. The structure of integrated hardware–software CPU with counters is presented. The paper presents how the designer can take advantage of the specific features of the FPGA devices to optimize both the utilization of resources and speed of realization of the particular blocks. Experimental results prove the high efficiency of the proposed solutions.