The paper discusses the design process of a full programmable logic controller implemented by means of FPGA device. The PLC is compliant with EN 61131-3 standard. It is equipped with a programmer that allows to transfer a program to the program memory of the controller, and the I/O controller which allows the exchange of information with the outside world, i.e. the signal modules. Some interesting aspects of instruction list and hardware architecture designing are presented, e.g. the PLC structure with a particular emphasis on central processing unit and memory map. The PLC is developed using one FPGA device as a combination of dedicated logic and soft-processor based parts. This gives an opportunity to develop interesting solutions. For example, using dual port RAM gives an opportunity to implement bit/word access without the necessity of masking bits. The paper presents a short description of a designed and written simple integrated development environment.

The paper discusses two methods of design of power optimized FSMs. Both methods use clock gating techniques. The main objective of the research was to write a program capable of generating automatic hardware description of finite-state machines in VHDL and testbenches to help power analysis. The creation of relevant output files is detailed step by step. The program was tested using the LGSynth91 FSM benchmark package. An analysis of the generated circuits shows that the second method presented in this paper leads to significant reduction of power consumption.

Power consumption in portable display systems is significantly affected by the energy cost of frame buffer memory accesses between the graphics processing unit (GPU) and the display processing unit (DPU). This paper presents the design and FPGA implementation of a visually lossless frame buffer codec based on the JPEG XS standard, intended for integration into on-chip systems to reduce memory bandwidth and associated power consumption. The codec is implemented in VHDL and targets the AMD Artix UltraScale+ xcau15p-2ffvb676e device. The codec supports both the standard ISO/IEC 21122 entropy coding path and a simplified non-standard Golomb–Rice mode intended for closed on-chip systems. Post-place-and-route results at PPC = 4 show that the Standard Precinct codec occupies 22.0% of device LUTs, while the proposed Golomb–Rice variant requires only 15.8%. At a compression ratio of 11:1, the codec achieves a PSNR of 40.20 dB, consistent with visually lossless operation reported for JPEG XS. Power estimation at 200 MHz shows that the Golomb–Rice mode reduces total codec power consumption by 44 mW (4.7%) relative to the Standard Precinct mode, with the decoder contributing the majority of this saving. The proposed solution is applicable to portable devices with built-in displays, including smartphones, tablets, and augmented reality headsets, where tile-based frame buffer compression is required without inter-frame dependencies.