Placement is essential in very large-scale integration (VLSI) physical design, as it directly affects the design cycle. Despite extensive prior research on placement, achieving fast and efficient placement remains challenging because of the increasing design complexity. In this paper, we comprehensively review the progress of placement optimization from the perspective of accelerating VLSI physical design. It can help researchers systematically understand the VLSI placement problem and the corresponding optimization means, thereby advancing modern placement optimization research. We highlight emerging trends in modern placement-centric VLSI physical design flows, including placement optimizers and learning-based predictors. We first define the placement problem and review the classical placement algorithms, then discuss the application bottleneck of the classical placement algorithms in advanced technology nodes and give corresponding solutions. After that, we introduce the development of placement optimizers, including algorithm improvements and computational acceleration, pointing out that these two aspects will jointly promote accelerating VLSI physical design. We also present research working on learning-based predictors from various angles. Finally, we discuss the common and individual challenges encountered by placement optimizers and learning-based predictors.

The security of smart devices is facing great challenges. This paper presents a new hybrid cipher framework suitable for such devices. Using software/hardware (SW/HW) co-design method, an efficient encryption/decryption and digital signature scheme based on SM2, SM3, SM4 algorithms is implemented. First, the framework is partitioned into software and hardware parts based on analysis result of a pure software solution and the hardware overhead under the conditions of design constraints. Second, the flow of the whole scheme and embedded algorithms are realized by SW/HW co-design. Finally, an improved implementation of SM2/3/4 algorithms is proposed to achieve higher efficiency. In this implementation, some SW/HW modules are parallelized to reduce the running time and enhance the performance. The proposed design is safe and can resist simple power analysis (SPA) attacks. Especially, the AHB bus interface IP and software scheduling approach are adopted in data transfer and manipulation. The design is taped-out on a silicon chip with SMIC 110nm technology process. The chip uses about 199K logic gates and 1mm areas. The operating frequency of the design is 36MHz and the chip consumes 23mW power. The comparison with similar previous works shows our proposed design is more efficient with speed increasing of more than ten percent.

A dual-core high-performance processor for Elliptic Curve Cryptography (ECC) in GF( ${p}$ ) over Generic Weierstrass Curves was presented in this brief. Firstly, an optimized radix-128 Montgomery modular multiplication algorithm was proposed. It takes 6 clock cycles to calculate modular multiplication, which promotes the speed of elliptic curve point-addition (PA) and elliptic curve point-doubling (PD). Secondly, a dual-core hardware architecture which includes PD core and PA core to calculate elliptic curve point-multiplication (PM) was developed. It can speed up the PM by adopting parallelism with different levels and optimizing the scheduling. Finally, a data transfer architecture between PA and PD cores was proposed which requires only a 1024-bit register. It improves the speed of PM. The proposed design consumes 996k gates and compute the PM in 0.017 ms on ASIC with a 90 nm standard cell library. Moreover, the proposed design is also implemented on FPGA (Virtex-6 platform), which consumes 182k LUTs and compute the PM in 0.056 ms.

Accelerators for convolutional neural networks (CNNs) based on field-programmable gate arrays (FPGAs) have drawn much attention in recent years. Two INT-8 multiplications are often implemented on a single digital signal processor (DSP) to improve DSP efficiency and performance. However, most of these works only use DSPs to implement multiplications and do not involve accumulations, which requires a lot of look-up tables (LUTs) and consequently leads to greater energy consumption. Furthermore, these works do not detail how to obtain two signed INT-8 multiplications with a DSP. This brief thus proposes a tiny accelerator for CNNs and a DSP-based processing element (PE) that is designed to implement two signed INT-8 multiply-and-accumulate (MAC) operations to reduce the overhead of LUTs. To allow the DSP to support two signed INT-8 MAC operations and avoid the large loss of accuracy caused by data overflow of partial sums (psum), we apply an efficient DSP optimization approach and a dynamic-precision quantization method. The accelerator is implemented on a Xilinx ZC706 FPGA device and achieves a DSP utilization efficiency $1.7\times $ to $7.3\times $ greater than state-of-the-art accelerators implemented on the same device. Furthermore, our accelerator offers $3.56\times $ greater energy efficiency than other FPGA-based accelerators.

The Internet-of-Things (IoT) has a security problem that has become increasingly significant. New architecture of SM3 which can be implemented in loT devices is proposed in this paper. The software/hardware co-design approach is put forward to implement the new architecture to achieve high performance and low costs. To facilitate software/hardware co-design, an AHB-SM3 interface controller (AHB-SIC) is designed as an AHB slave interface IP to exchange data with the embedded CPU. Task scheduling and hardware resource optimization techniques are adopted in the design of expansion modules. The task scheduling and critical path optimization techniques are utilized in the compression module design. The proposed architecture is implemented with ASIC using SMIC 130 nm technology. For the purpose of comparison, the proposed architecture is also implemented on Virtex 7 FPGA with a 36 MHz system clock. Compared with the standard implementation of SM3, the proposed architecture saves the number of registers for approximately 3.11 times, and 263 Mbps throughput is achieved under the 36 MHz clock. This design signifies an excellent trade-off between performance and the hardware area. Thus, the design accommodates the resource-limited IoT security devices very well. The proposed architecture is applied to an intelligent security gateway device.

Embedded hardware accelerator with limited resources is increasingly employed in security areas. To accelerate system-on-chip (SoC) design, an efficient HW/SW co-design approach and validation platform become extremely important. The Electronic System Level Simulator (ESL) based on SystemC is the primary solution for fast hardware modeling and verification. However, most existing simulators cannot achieve a better trade-off between accuracy and performance, and none of the specific ESL simulators are proposed for cryptographic SoCs. To this end, this brief proposes a virtual prototype (VP) with integrated cryptographic accelerators for a cryptographic SoC based on RISC-V to accelerate the functional and performance simulation of the SoC. The VP is designed as an extensible and configurable platform dedicated to cryptographic SoC using an efficient HW/SW co-design approach. To accurately emulate real hardware, the flexible AHB-TLM interface and core timing model are presented. Compared to the RTL simulation, our custom VP performs about 10-450 times faster than the RTL simulation, and the simulation error is only about 4%. Our code is available at https://github.com/LX-IC/VP.