This paper presents a methodology to design and prototype an FPGA-based fully digital controller for power electronics systems. A Top-down methodology is used to study step by step the digital adaptation and implementation of the control algorithm. Finally, an experimental FPGA in the loop prototype is achieved, based on MATLAB/SimPower Systems and Altera DSP Builder mixed simulation tools. Modeling, mixed simulation and FPGA in the loop prototyping are achieved in a unique design environment. An application using the proposed methodology is studied: a fully digital controller for a single- phase parallel active power filter. The controller is described and the control algorithm examined with FPGA in the loop prototyping.

A new design method of an all‐digital automatic gain control easy to implement is described and tested. The discretisation of the instantaneous gain provides a recursive form that merges the exponential function with the level detection. The first proposed circuit is well adapted for a software implementation. It comprises a simple control loop and two multipliers. It does neither contain digital filter nor divider and its setting only requires a loop gain parameter. Some tests were conducted on real digital audio signals with a dynamic range of 80 dB and they validate this approach. Under some conditions, the second circuit can even be simpler since it requires only one multiplier. It is well adapted to an field programmable gate array (FPGA) implementation for high speed signal processing.

This paper presents a totally digital phase locked loop (PLL) used for the recovery of a MPEG-2 decoder clock. The All Digital PLL (ADPLL) is implemented with a frequency synthesizer based on a new technique for phase shifting, avoiding the phase accumulation of ADPLL using a ring oscillator or avoiding the multiphase generation if a delay-locked loop (DLL) is used. The strongest point of the proposed configuration is the possibility of implementing as many ADPLLs as needed in a single circuit, in the limit of the circuit resources, without additional external circuit. The transfer characteristic, frequency resolution and jitter performance are computed and discussed. Then, the ADPLL resources and the ADPLL performances in term of time response and jitter are reported.

In the context of smart cities, monitoring pedestrian and vehicle movements is essential to recognize abnormal events and prevent accidents. The proposed method in this work focuses on analyzing video streams captured from a vertically installed camera, and performing contextual road user detection. The final detection is based on the fusion of the outputs of three different convolutional neural networks. We are simultaneously interested in detecting road users, their motion, and their location respecting the static environment. We use YOLOv4 for object detection, FC-HarDNet for background semantic segmentation, and FlowNet 2.0 for motion detection. FC-HarDNet and YOLOv4 were retrained with our orthophotographs dataset. The last step involves a data fusion module. The presented results show that the method allows one to detect road users, identify the surfaces on which they move, quantify their apparent velocity, and estimate their actual velocity.