As the standard complementary metal-oxidesemiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18-μm CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution.

In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

Short channel MOSFET exhibits the characteristics of wide bandwidth and low DC gain. A low DC gain causes a high gain error and a narrow output linear range in the closed loop. The DC gains can be improved by using the cascade structure, but frequency compensation is required due to the increase in the number of poles. The output nodes of each stage in a cascade Common-Source amplifier have a cascade of zero, and this zero is cancelled out by the input node of the next stage. This paper proposes a three-stage operational amplifier (op-amp) with frequency compensation using cascade zero. This op-amp was implemented in the 180 nm CMOS technology and achieved 86.96 MHz unity–gain frequency, 51.7° phase margin at 32 pF load capacitor and 99.83 dB DC gain, that is, a 36.21 dB improvement over a two-stage op-amp with the same power consumption. The op-amp consumed 7.74 mW with a supply voltage of 1.8 V.

A radiation-hardened instrumentation amplifier (IA) that allows precise measurement in radiation environments, including nuclear power plants, space environments, and radiation therapy rooms, was designed and manufactured, and its characteristics were verified. Most electronic systems are currently designed using silicon-based complementary metal-oxide semiconductor (CMOS) integrated circuits (ICs) to achieve a highly integrated low-power design. However, fixed charges induced in silicon by ionization radiation cause various negative effects, resulting in, for example, the generation of leakage current in circuits, performance degradation, and malfunction. Given that such problems in radiation environments may directly lead to a loss of life or environmental contamination, it is critical to implement radiation-hardened CMOS IC technology. In this study, an IA used to amplify fine signals of the sensors was designed and fabricated in the 0.18 μm CMOS bulk process. The IA contained sub-circuits that ensured the stable voltage supply needed to implement system-on-chip (SoC) solutions. It was also equipped with special radiation-hardening technology by applying an I-gate n-MOSFET that blocks the radiation-induced leakage currents. Its ICs were verified to provide the intended performance following a total cumulative dose of up to 25 kGy(Si), ensuring its safety in radiation environments.

In the present study, the layout structure of an n-MOSFET, which is vulnerable to radiation, was designed in a different way to enhance its tolerance to radiation. Radiation damage assessment was conducted using modeling and simulation (M&S) techniques before actual semiconductor process fabrication and radiation tests to verify its tolerance properties. Based on the M&S techniques, the role of each layer was determined to improve the radiation tolerance of semiconductors, and the layout design of an n-MOSFET with enhanced radiation tolerance was optimized. The optimized radiation-tolerant n-MOSFET design was implemented in the 0.18-um CMOS bulk process, and radiation exposure tests were conducted on the device. A cumulative radiation dose up to 2 Mrad(Si) was applied to verify its radiation-tolerant performance. Developing new devices using M&S techniques for radiation damage assessment allows reliable estimates of their electrical and radiation-tolerant properties to be obtained in advance of the actual manufacturing process, thereby minimizing development costs and time.