In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance.

In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R _RESET/R _SET = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If R _RESET/R _SET is increased to 500, we can increase the passive array size up to 1000 × 1000 with maintaining the read sensing margin lager than 10% of V_DD. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.

Memristive devices such as memristors that have been intensively studied for their possibilities as a strong candidate for future memories are known to have two problems. First, they need a large current in write operation, and second their process-V -temperature (PVT) variations are large compared with the conventional DRAM and FLASH memories. Moreover, the large writing current can be magnified with PVT variations. In this letter, a new write circuit is proposed to prevent unnecessary power loss by using a self-adjusting circuit for properly sizing the writing pulsewidth, thereby minimizing power consumption. The simulation results show that self-adjusting the pulsewidth can save power by 76% on average, compared to the conventional write circuit with a fixed pulsewidth.

In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. In the new twin crossbar, we use two identical memristor arrays instead of using the previous complementary memristor arrays of M ⁺ and M ^- . Thereby, we can apply the discrete cosine transform (DCT) algorithm to reduce the number of low-resistance state (LRS) cells in the two identical M ⁺ arrays. With the reduced number of LRS cells in two M ⁺ arrays, the power consumption in the crossbar can be significantly saved compared to the previous complementary crossbar that is not suitable to DCT. When the number of discarded coefficients in the DCT matrix is 56.25%, 67.19%, 76.56%, and 84.38%, the power consumption of the new twin crossbar is reduced by 51.7%, 61.3%, 69.9%, and 77.4%, respectively, compared to the previous complementary one.

For realizing neural networks with binary memristor crossbars, memristors should be programmed by high-resistance state (HRS) and low-resistance state (LRS), according to the training algorithms like backpropagation. Unfortunately, it takes a very long time and consumes a large amount of power in training the memristor crossbar, because the program-verify scheme of memristor-programming is based on the incremental programming pulses, where many programming and verifying pulses are repeated until the target conductance. Thus, this reduces the programming time and power is very essential for energy-efficient and fast training of memristor networks. In this paper, we compared four different programming schemes, which are F-F, C-F, F-C, and C-C, respectively. C-C means both HRS and LRS are coarse-programmed. C-F has the coarse-programmed HRS and fine LRS, respectively. F-C is vice versa of C-F. In F-F, both HRS and LRS are fine-programmed. Comparing the error-energy products among the four schemes, C-F shows the minimum error with the minimum energy consumption. The asymmetrical coarse HRS and fine LRS can reduce the time and energy during the crossbar training significantly, because only LRS is fine-programmed. Moreover, the asymmetrical C-F can maintain the network’s error as small as F-F, which is due to the coarse-programmed HRS that slightly degrades the error.