One of the most important topics in the field of wireless sensor networks is the development of approaches to improve network lifetime. In this paper, an energy-efficient control and routing protocol for wireless sensor networks is presented. This algorithm is based on reinforcement learning for energy management in the network. This protocol seeks to optimize routing policies to maximize the long-term reward received by each node, using reinforcement learning, which is a machine learning approach. In order to improve the lifetime of wireless sensor network, three energy management approaches have been proposed. The first approach is to navigate correctly using reinforcement learning to reduce the length of the routes and to improve energy consumption. The second approach is to exploit a sleep scheduling technique to improve node energy consumption. The last approach is used to restrict data transmission of each node based on the received data change rate. Simulation results show that in terms of network lifespan, the proposed method significantly outperforms previous reported methods.

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain–machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.

This paper presents a six-transistor bitcell SRAM with pMOS access transistor. Utilizing pMOS access transistor results in lower zero-level degradation (ZLD) and, hence, higher read stability. In addition, the access transistor connected to the internal node holding VDD acts as a stabilizer and counter balances the effect of ZLD. In order to improve the writability, wordline (WL) boosting is exploited. WL boosting also helps to compensate the lower speed of the pMOS access transistor compared with nMOS transistor. To verify our design, a 2-kb SRAM is fabricated in the TSMC 65-nm CMOS technology. Measurement results show that the maximum operational frequency of the test chip is at 3.34 MHz at 290 mV. The minimum energy consumption is measured as 1.1 fJ/bit at 400 mV.

The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in the subthreshold region with no extra energy cost. The optimum pMOS-to-nMOS width ratio is obtained and compared through three approaches: 1) finding the maximum current-over-capacitance ratio of a biased transistor; 2) deriving an analytical expression by minimizing the delay of an inverter; and 3) simulating different CMOS logic gates in the subthreshold region. Simulation results illustrate that in the subthreshold region, the frequency attains its maximum at the optimum pMOS-to-nMOS width ratio independent of the supply voltage. Using this optimum value in designing a carry-look-ahead adder improves the propagation delay, energy consumption, and energy-delay product by up to 33%, 36%, and 57%, receptively, compared with when the conventional pMOS-to-nMOS width ratio (in the superthreshold region) is used. We verified our analytical model by performing circuit simulations in four CMOS technologies (TSMC 180 nm, IBM 130 nm, TSMC 90 nm, and ST 65 nm).

This paper proposes a real-time thermal monitoring method using embedded integrated sensor interfaces dedicated to industrial integrated system applications. Industrial sensor interfaces are complex systems that involve analog and mixed signals, where several parameters can influence their performance. These include the presence of heat sources near sensitive integrated circuits, and various heat transfer phenomena need to be considered. This creates a need for real-time thermal monitoring and management. Indeed, the control of transient temperature gradients or temperature differential variations as well as the prediction of possible induced thermal shocks and stress at early design phases of advanced integrated circuits and systems are essential. This paper addresses the growing requirements of microelectronics applications in several areas that experience fast variations in high-power density and thermal gradient differences caused by the implementation of different systems on the same chip, such as the new-generation 5G circuits. To mitigate adverse thermal effects, a real-time prediction algorithm is proposed and validated using the MCUXpresso tool applied to a Freescale embedded sensor board to monitor and predict its temperature profile in real time by programming the embedded sensor into the FRDM-KL26Z board. Based on discrete temperature measurements, the embedded system is used to predict, in advance, overheating situations in the embedded integrated circuit (IC). These results confirm the peak detection capability of the proposed algorithm that satisfactorily predicts thermal peaks in the FRDM-KL26Z board as modeled with a finite element thermal analysis tool (the Numerical Integrated elements for System Analysis (NISA) tool), to gauge the level of local thermomechanical stresses that may be induced. In this paper, the FPGA implementation and comparison measurements are also presented. This work provides a solution to the thermal stresses and local system overheating that have been a major concern for integrated sensor interface designers when designing integrated circuits in various high-performance technologies or harsh environments.

Efficient design and optimization of flip-flops can significantly affect overall circuit performance as they have many applications in digital systems which can impact the overall power consumption and timings of the emerging system on chips (SOCs). In this paper, modeling, design, and optimization of transmission gate-based master-secondary positive-edge-triggered flip-flop (TGFF) in 16 nm complementary metal-oxide semiconductor (CMOS) is proposed. The proposed deep neural network (DNN)-based optimization method first generates an accurate model for different performance metrics by using the training data obtained from transistor-level models which are over 100 times faster than them. Then, these accurate DNN-based models are used to optimize design goals such as dynamic and static power, setup time, and propagation delay (Data to Output). Using these fast, accurate models significantly speeds up the design procedure and leads to a considerably more optimized design. Additionally, as the DNN is a universal approximator that can catch any nonlinear input-output relationship, the proposed method can be used to optimize circuits for any performance metric even if no analytical formula is available. Additionally, circuit design based on the proposed method is automated which facilitates the tasks of circuit designers.