This study presents a topology for cascaded multilevel inverter (MLI). Each module is made up of H‐ and half‐bridges, two isolated equal dc sources and a bidirectional auxiliary circuit. One leg of the H‐bridge and the half‐bridge are cut and the corresponding terminals are connected to the both ends of an equal split dc source. The free ends of the half‐bridge are connected together to form a common output node of the inverter. The auxiliary circuit is inserted between the midpoint of the split dc sources and this very output node. The output point of the uncut leg of the H‐bridge forms the remaining output node. With this circuit arrangement, proper control of the switches in the bridges and the auxiliary circuit, in each cascaded cell, can produce nine output voltage levels. A comparison is made between the proposed inverter, classical CHB and some of the recent developed MLI topologies with respect to specified figure of merits, as well as the per unit power losses. For two cascaded modules, simulation and experimental verifications are carried out on the proposed inverter topology for an R‐L load; adequate results are presented.

This study proposes a single‐phase, 9‐level, cascade multilevel inverter topology. The multicarrier, phase disposition pulse width modulation scheme is employed to generate the gating signals for the power switches. Operational principles with switching functions are given. By controlling the modulation index, the desired number of levels: 3, 5, 7 and 9, of the inverter's output voltage can be achieved. For modulation indices of: 0.24, 0.4, 0.6 and 0.8, the proposed inverter configuration was subjected to an R–L load and the respective numbers of output voltage level were synthesized. Fast Fourier transform analyses of the output voltage waveforms were carried out and the corresponding THD values were obtained. For a modulation index of 0.8, a THD value of 10.12% has been achieved in the output voltage waveform of the proposed inverter configuration. Comparison of the proposed inverter configuration and the classical single‐phase topologies is given based on the power circuit component count. Moreover, analysis of the conduction power losses in the power semiconductor switches of the proposed inverter topology is given. To verify the performance of the proposed inverter architecture, simulations and experiments are carried out on a 2.12 kW rated prototype of the proposed inverter for an R–L load; and adequate results are presented.

Space vector pulsewidth modulation (SVPWM) algorithms for cascaded H-bridge multilevel (CHB ML) inverter usually provide the possibility of using several combinations of active voltage vectors to generate the same output voltage vector. For preselected H-bridges, some of them may generate output voltages opposite to the assumed direction. This results in the change of the dc-link voltages of these H-bridges in the opposite direction to the assumed direction in the ordering algorithm. Consequently, these algorithms are characterized by undue constraints and narrow possibilities of dc-link voltage balancing. In the proposed control algorithm, CHB ML inverter is treated as groups of successively activated three-level inverters; depending on the length of the reference voltage vector. These three-level inverters consist of three H-bridges selected from each phase. The proposed extended selection method enables firm-grip control of the dc-link voltages. For a given direction of phase currents, the possibility of using H-bridges with lowest and highest dc-link voltages is simultaneously analyzed. Additionally, each of the three-level inverters is controlled by one of three proposed alternative modulation methods for which both the attainable output voltage vectors and unbalanced dc-link voltages are predicted. Simulation and experimental results confirm the correctness of the algorithm execution.

Multiplicity of the triangular carrier signals is a criterion for the extension of sinusoidal pulse-width modulation, SPWM, to a number of output voltage levels per phase-leg in cascaded H-bridge (CHB) multilevel inverter (MLI). Considering medium and high voltage applications where appreciable number of output voltage levels from CHB MLI is needed, commensurate high number of carrier signals in either classical level- or phase-shifted SPWM scheme for this inverter is inevitable. High-quality output waveforms from CHB MLI system demands precise synchronization of these multi-carrier signals. Sampling issues, memory constraints and computational delays pose difficulties in achieving this synchronization for real-time digital implementation. This study presents a PWM template for CHB MLI. The developed control concept generates adequate modulation templates for CHB inverter wherein a sinusoidal modulating waveform is modified to fit in a single triangular carrier signal range. These templates can be used on CHB inverter of any level with no further control modification. Nearly even distribution of switching pulses, equal sharing of the overall real power among the constituting power switches and enhanced output voltage quality were achieved with the proposed modulation. For a 3-phase, 7-level CHB, simulation and experimental results, for an R-L load, were presented.

Given the recent available IGBT switch modules up to 6.5 kV, 1200 A rating, the prospect of the diode-free variant topology of the three-level neutral-point-clamped (3-level, T-type) inverter in certain medium voltage applications is bright; due to its small part count and low conduction losses compared to the diode-clamped NPC inverter. However, within this voltage range, the input dc voltage rating of 50% of the switches per inverter phase-leg still poses limitations to the deployment of 3-level T-type inverter. In view of these limitations, a reconfigured four-switch per phase-leg power circuit for 3-level inverter (F-type) is presented in this paper. The common node of the bidirectional switch in T-type inverter is explored to have only one power switch rated at input dc voltage and 3 switches rated at half the input dc voltage, per inverter-leg. This reduced voltage stress has inverter cost and loss implications. The performances and competitiveness of the three-level, F-type inverter are analyzed in detail and demonstrated with a hardware prototype. Results reveal that it has the potentials of being considered a real alternative to 3-level, T-type inverters for certain low- and medium-voltage applications.

In the sensorless control system of an induction machine, the rotor speed value is not measured but reconstructed by an observer structure. The rotor speed value can be reconstructed by the classical adaptive law with the integrator. The second approach, which is the main contribution of this article, is the nonadaptive structure without an integrator. The proposed method of the rotor speed reconstruction is based on an algebraic relationship – the rank of the mathematical model of the observer system is not increased. However, the problem with the stabilization of the observer structure does exist. For near to zero rotor speed or in the regenerating mode of an induction machine, the speed observer structure can be unstable. Therefore, in this article, the new stabilization functions are proposed. The stability is provided by the Lyapunov theorem and the practical stability theorems in which the uncertainty of parameters is considered. In the proposed solution, the newly introduced stabilization functions guarantee observer stability during both the motoring and regenerating conditions at the chosen low rotor speed ranges and for different load torque values. All the theoretical considerations were confirmed by simulation and experimental tests during the chosen working modes and uncertainties of nominal parameters of the induction machine.