Given the recent available IGBT switch modules up to 6.5 kV, 1200 A rating, the prospect of the diode-free variant topology of the three-level neutral-point-clamped (3-level, T-type) inverter in certain medium voltage applications is bright; due to its small part count and low conduction losses compared to the diode-clamped NPC inverter. However, within this voltage range, the input dc voltage rating of 50% of the switches per inverter phase-leg still poses limitations to the deployment of 3-level T-type inverter. In view of these limitations, a reconfigured four-switch per phase-leg power circuit for 3-level inverter (F-type) is presented in this paper. The common node of the bidirectional switch in T-type inverter is explored to have only one power switch rated at input dc voltage and 3 switches rated at half the input dc voltage, per inverter-leg. This reduced voltage stress has inverter cost and loss implications. The performances and competitiveness of the three-level, F-type inverter are analyzed in detail and demonstrated with a hardware prototype. Results reveal that it has the potentials of being considered a real alternative to 3-level, T-type inverters for certain low- and medium-voltage applications.

A simple hybridized pulsewidth modulation (PWM) algorithm for three- and multiphase three-level neutral point clamped (NPC) inverters is proposed. The proposed solution is based on classical space vector PWM (SVPWM) algorithms for two-level inverters but can also be based on sinusoidal PWM with min–max injection. An additional level of output voltage is obtained by modifying the resulting switching patterns taking into account the actual dc-link voltages. In the case of SVPWM algorithms, such an approach eliminates the need to find the subsector where the reference voltage vector is located. It is also not necessary to analyze the changes in the position and length of active vectors in the case of dc-link voltage imbalance. DC-link voltage balancing is achieved by modifying the switching pattern, taking into account the values and direction of phase currents and actual dc-link voltages. Also, the algorithm optimizes the switching pattern and eliminates unnecessary switching instances. The proposed approach utilizes both space vector analysis and independent control of individual inverter-legs. The latter is peculiar to carrier-based PWM; hence, the proposed solution is termed hybridized PWM. Presented experimental tests and results validated the proposed control concept and algorithm for three- and multiphase NPC inverters.

In space vector pulsewidth modulation (SVPWM) algorithms for multiphase two-level voltage source inverters (VSI), the components of active vectors in all orthogonal spaces have to be calculated within the processor and stored in its memory. These necessitate intensive computational efforts of the processor and large memory space. This article presents a hybridized SVPWM for multiphase two-level VSI. In this algorithm, elements of the vector coefficient inverse matrix are calculated once outside the inverter processor and treated as constant values; this reduces the computational efforts of the processor and memory space. This scheme reverses the computational steps used in classical SVPWM. Arbitrarily pre-selected active vectors (for any position and amplitude of the reference vectors) with durations determined using classical SVPWM concept are utilized. The durations of switching vectors are analyzed and the switching sequences in individual inverter phases are optimized to reduce the number of commutations. This approach demonstrates that resignation from classical analytical method in multiphase two-level VSI enables the creation of simplified modulation algorithm. This modulation strategy enables an independent generation of multiple output voltage vectors with independent rotating speed, lengths, and positions. Experimental validation of the algorithm was carried out on two-level five-phase VSI with RL load.

Increasing the voltage of energy sources, such as photovoltaic (PV), fuel cells, and battery storage units, requires a voltage-boosting technique. This paper introduces an efficient switched-capacitor multilevel inverter (SC-MLI) capable of generating a boosted seven-level output voltage. The key advantages of this topology include the inherent self-balancing of capacitor voltages without the need for auxiliary balancing techniques. Additionally, the proposed SC-MLI offers numerous features such as lower voltage stress, improved efficiency, and reduced overall cost. The proposed topology has been evaluated based on parameters such as component count, THD, cost, and efficiency. Experimental validation was conducted on a 1.0 kW prototype setup under varying modulation index and sudden load changes. Finally, a thorough comparison with state-of-the-art seven-level multilevel inverters highlighted the features of the proposed topology.

This article presents a carrier-based pulse-width modulation (PWM) template for a 5-level, H bridge-based cascaded multilevel inverter (MLI). The developed control concept generates adequate modulation template for this inverter topology wherein a sinusoidal modulating waveform is modified to fit in a single triangular carrier signal range. With this modulation approach, classical multiplicity and synchronization of the triangular carrier signals criterion for the extension of sinusoidal pulse-width modulation, SPWM, to several cascaded 5-level, H-bridge-based MLI topology are removed. The proposed template can be used on the inverter configuration of any level with no further control modification. Nearly even distribution of switching pulses and equalized individual cascaded cell output power were achieved with the proposed modulation scheme. Three 5-level, H-bridge-based MLI units were cascaded for 1-phase, 13-level inverter operation; simulation and experimental results are adequately presented.

This article presents a modified sinusoidal pulse-width modulation (SPWM) scheme for a five-phase, three-level neutral-point-clamped inverter. The modulation scheme deploys a modified min–max function to inject the zero-sequence components into the reference modulating signals; hence enabling the effective utilization of the DC-link voltage. Balanced split-input DC-link voltages were achieved through further incorporation of adjustable voltage-dependent variables into the reference signals. The dynamic performance of the control approach is demonstrated through simulations and experiments on a laboratory inverter prototype; the results are well presented.