We present a new programmable neighborhood mechanism for hardware implemented Kohonen self-organizing maps (SOMs) with three different map topologies realized on a single chip. The proposed circuit comes as a fully parallel and asynchronous architecture. The mechanism is very fast. In a medium sized map with several hundreds neurons implemented in the complementary metal-oxide semiconductor 0.18 μm technology, all neurons start adapting the weights after no more than 11 ns. The adaptation is then carried out in parallel. This is an evident advantage in comparison with the commonly used software-realized SOMs. The circuit is robust against the process, supply voltage and environment temperature variations. Due to a simple structure, it features low energy consumption of a few pJ per neuron per a single learning pattern. In this paper, we discuss different aspects of hardware realization, such as a suitable selection of the map topology and the initial neighborhood range, as the optimization of these parameters is essential when looking from the circuit complexity point of view. For the optimal values of these parameters, the chip area and the power dissipation can be reduced even by 60% and 80%, respectively, without affecting the quality of learning.

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18-μm technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 μm ² . When operating in the L2 mode, the circuit dissipates 85 μW of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 μW from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

In this paper we present an example design process of filters used in automotive industry. Signal preprocessing is very important operation in active safety algorithms. Such algorithms usually take into account the vehicle state that includes position, velocities and accelerations of the car. On the basis of these data, as well as the parameters and trajectories of external objects “observed” by the car, the algorithms make decisions about various safety actions. Designer of such algorithms must assure an appropriate quality of such signals, which usually means a proper filtering. In this paper we focus on selected important aspects of the filter design process. The main objectives of the presented investigations is to obtain such filters that ensure a sufficient rejection of undesired components from the signal and at the same time that do not introduce too high delay to the processed signals. In our work we consider linear filters such as finite impulse response (FIR) and infinite impulse response (IIR) filters of different types and lengths, as well as nonlinear filters - in this case median filters. Selection of these filters results from the parameters of the signal. Since the filters have to be finally implemented in low cost and low power devices, in the paper we focus also on hardware implementation issues. Selected filters have been implemented in Field Programmable Gate Array to verify the concept.