The bandgap dependence on the number of atomic layers of some families of 2D materials can be exploited to engineer and use lateral heterostructures (LHs) as high-performance Field-Effect Transistors (FET). This option can provide very good lattice matching as well as high heterointerface quality. More importantly, this bandgap modulation with layer stacking can give rise to steep transitions in the density of states (DOS) of the 2D material, that can eventually be used to achieve sub-60 mV/decade subthreshold swing in LH-FETs thanks to an energy-filtering source. We have observed this effect in the case of a PdS₂ LH-FET due to the particular density of states of its bilayer configuration. Our results are based on ab initio and multiscale materials and device modeling, and incite the exploration of the 2D-material design space in order to find more abrupt DOS transitions and better suitable candidates.

We explore the performance limits of monolayer InSe n-type and p-type FETs by means of first-principle simulations of carrier transport in nanoscale devices. We evaluate the impact on device performance of different device parameters, such as channel length, oxide thickness, and gate underlap. Finally, we assess the operation of a 32-bit CMOS ALU, based on InSe FETs with 10-nm channel length, for both high-performance and low-power applications, and find promising figures of merit with respect to CMOS and other beyond-CMOS proposals.

We propose two transistor concepts based on lateral heterostructures of monolayer ${\mathrm{MoS}}_2$, composed of adjacent regions of $1T$ (metallic) and $2H$ (semiconducting) phases, inspired by recent research showing the possibility to obtain such heterostructures by electron-beam irradiation. The first concept, the lateral heterostructure field-effect transistor, exhibits the potential of better performance with respect to the foreseen evolution of CMOS technology, both for high-performance and low-power applications. Performance potential is evaluated by means of detailed multiscale materials and device simulations. The second concept, the planar barristor, also exhibits potential competitive performance with CMOS, and an improvement of orders of magnitude in terms of the main figures of merit with respect to the recently proposed vertical barristor.

An analytical compact model for 2-D crystal FETs is proposed. It provides an explicit expression for the drain current as a function of the gate and drain voltages considering Fermi-Dirac statistics and drift-diffusion transport. The model is applicable to $n$-type or $p$-type symmetric and asymmetric double gate devices as well as single gate transistors. It is validated against experimental results and can be used to explore in a simple but accurate fashion the physics and the performance limits of 2-D crystal FETs.