Secure and reliable information flow is one of the main challenges in social IoT and mobile networks. Information flow and data integrity is still an open research problem. In this paper, we develop new methods of constructing systematic and regular Low-Density Parity-Check Matrices (LDPCM), inspired by the structure of the Sarrus method and geometric designs. Furthermore, these codes have cyclic structure and therefore, are less complex in computation and also require less memory in hardware implementation. Besides, an optimal method of post-processing for deleting girths four is presented. Numerical results show that the codes constructed by these methods perform well over the additive white Gaussian noise (AWGN) channel when decoded with the sum-product LDPC iterative algorithms. The proposed methods can be very efficient in terms of reducing memory consumption and improving the convergence speed of the decoder particularly in IoT and mobile networks.

The need for ultra-low power and area-efficient analog-to-digital converters (ADCs) is pushing towards the use of low-voltage (LV) dynamic clocked comparators to maximize power efficiency and speed. In this paper, a delay analysis for a conventional body-driven LV dynamic comparator is presented. Then based on the analysis results, the circuit of a conventional body-driven comparator is modified for fast operation even in small supply voltages. Simulation results in 90nm CMOS technology reveal that comparator delay time is remarkably reduced. The maximum clock frequency of the proposed comparator can be increased to 333 MHz and 50 MHz at supply voltages of 0.5V and 0.35V, while consuming 2.3μW and 184nW, respectively. The standard deviation of the input-referred offset voltage is 5.1mV at 0.5V supply.

Power dissipation is known as the most notable limiting factor in all nano-electronic design techniques including Quantum-dot Cellular Automata (QCA). The familiar reversible computing approach is used as a reasonably reliable solution, mitigating power dissipation. This study presents, a comprehensive multi-objective method for designing R-Fs in emerging QCA technology. The results are investigated in both logical and layout levels, in detail. The results verify that the approach offered in this study has advantage over the most efficient approaches available in the literature by far. This comparison can be made on various parameters ranging from area, complexity (cell amount), delay (clocking zones), and to even logical levels including levels, Control inputs, the number of majority and NOT gates.