Implementing applicable security measures into system engineering applications is still one of the most challenging processes in building secure infrastructure. This process needs to consider a variety of security attributes to support securing system components against numerous cyberattacks that could exploit vulnerable points in the system. The redundancy in these attributes is also another challenge that could degrade system functionality and impact the availability of the system’s services. Therefore, it is crucial to choose appropriate security properties by considering their ability to address cyber threats with minimal negative impacts on the system’s functionality. This process is still subjected to inconsistencies due to ad- oc determinations by a specialist. In this work, we propose a novel algorithm for optimizing the implementation of security mechanisms in IoT applications for the agricultural domain to ensure the effectiveness of the applied mechanisms against the propagation of potential threats. We demonstrate our proposed algorithm on an IoT application in the farming domain to see how the algorithm helps with optimizing the applied security mechanisms. In addition, we used THREATGET to analyze cyber risks and validate the optimized security attributes against the propagation of cyber threats.

Code conversion, encompassing translation, optimization, and generation, is becoming increasingly critical in information systems and the software industry. Traditional validation methods, such as test cases and code coverage metrics, often fail to ensure the correctness, completeness, and equivalence of converted code to its original form. Formal verification emerges as a crucial methodology to address these limitations. Although numerous surveys have explored formal verification in various contexts, a significant research gap exists in pinpointing appropriate formal verification approaches to code conversion tasks. This paper provides a detailed survey of formal verification techniques applicable to code conversion. This survey identifies the strengths and limitations of contemporary adopted approaches while outlining a trajectory for future research, emphasizing the need for automated and scalable verification tools. The novel categorization of formal verification methods provided in this paper serves as a foundational guide for researchers seeking to enhance the reliability of code conversion processes.

FPGAs are becoming more popular in the domain of safety-critical applications (such as space applications) due to their high performance, re-programmability and reduced development cost. Such systems require FPGAs with self-detection and self-repairing capabilities in order to cope with errors due to the harsh conditions that usually exist in such environments. In this paper, a new dynamic fault recovery technique is proposed using the runtime partial reconfiguration (PR) property in FPGAs. It focuses on open interconnect faults and relies on specifying a Partially Reconfigurable block in the FPGA that is only used during the recovery process after the failure of the first module in the system. The technique uses only one location to recover from errors in any of the FPGA's modules. Accordingly, it requires less area overhead when compared to other techniques.

Fault-Tolerance is quickly becoming a very important issue in the design of industrial automation systems. This paper addresses this issue in the context of temporary failures occurring in harsh industrial environments. The Fault-Tolerant design of sensors and controllers is investigated for both the In-Loop and Sensor-to-Actuator architectures. Processing is implemented on FPGAs whenever possible. Triple Modular Redundancy (TMR) is used to implement sensors for fast varying applications while Temporal Redundancy (TR) is used for sensors for slow varying applications in order to reduce cost without affecting system reliability. Dynamic Partial Reconfiguration (DPR) is used for fault recovery. Reliability models are developed for all Fault-Tolerant blocks to help system designers with the choice of the Fault-Tolerant techniques to be implemented. Two case studies are carried out with different numbers of fast and slow sensors. System reliabilities are calculated for both conventional and hybrid NCS systems. Results show that the proposed technique results in a cost-effective system at the expense of a very slight decrease in reliability.

Nowadays, FPGAs play a great role in electronic circuits design especially in implementing critical applications. As a result, the need for adding fault-tolerance to FPGAs becomes very important. In this paper, a fault-tolerant technique and associated modifications on FPGA architecture are proposed. This technique can detect and recover from open faults in programmable interconnects. It was successfully simulated using an FPGA-based simulator.