Addressing data anomalies (e.g., garbage data, outliers, redundant data, and missing data) plays a vital role in performing accurate analytics (billing, forecasting, load profiling, etc.) on smart homes’ energy consumption data. From the literature, it has been identified that the data imputation with machine learning (ML)-based single-classifier approaches are used to address data quality issues. However, these approaches are not effective to address the hidden issues of smart home energy consumption data due to the presence of a variety of anomalies. Hence, this paper proposes ML-based ensemble classifiers using random forest (RF), support vector machine (SVM), decision tree (DT), naive Bayes, K-nearest neighbor, and neural networks to handle all the possible anomalies in smart home energy consumption data. The proposed approach initially identifies all anomalies and removes them, and then imputes this removed/missing information. The entire implementation consists of four parts. Part 1 presents anomaly detection and removal, part 2 presents data imputation, part 3 presents single-classifier approaches, and part 4 presents ensemble classifiers approaches. To assess the classifiers’ performance, various metrics, namely, accuracy, precision, recall/sensitivity, specificity, and F1 score are computed. From these metrics, it is identified that the ensemble classifier “RF+SVM+DT” has shown superior performance over the conventional single classifiers as well the other ensemble classifiers for anomaly handling.

Analog-to-digital circuit converts an analog signal having continuous-time and continuous-amplitude to a discrete-time and discrete-amplitude digital signal. A comparator is a vital block in any analog-to-digital circuit. The comparators play a crucial part in the analog to digital conversion. This paper puts forth the design of hysteresis comparator in 90-nm CMOS technology. The proposed comparator reduces the occurrence of noisy output and has high speed, in comparison to the conventional comparator. The circuit design and analysis has been done using Cadence.

High-quality data are always desirable for superior decision-making in smart buildings. However, latency issues, communication failures, meter glitches, etc., create data anomalies. Especially, the redundant/duplicate records captured at the same time instants are critical anomalies. Two such cases are the same timestamps with the same energy consumption reading and the same timestamps with different energy consumption readings. This causes data inconsistency that deludes decision-making and analytics. Thus, such anomalies must be properly identified. So, this paper performs an enumeration of redundant data anomalies in smart building energy consumption readings using an analytical approach with 4-phases (sub-dataset extraction, quantification, visualization, and analysis). This provides the count, distribution, type, and correlation of redundancies. Smart buildings’ energy consumption dataset of Darmstadt city, Germany, was used in this study. From this study, the highest count of redundancies is observed as 5060 on 26 January 2012 with the average count of redundancies at the hour level being 211 and the minute level being 7. Similarly, the lowest count of redundancies is observed as 89 on 24 January 2012. Further, out of these 5060 redundancies, 1453 redundancies are found with the same readings and 3607 redundancies are found with different readings. Additionally, it is identified that there are only 14 min out of 1440 min on 26 January 2012 without having any redundancy. This means that almost 99% of the minutes in the day possess some kind of redundancies, where the energy consumption readings were recorded mostly with two occurrences, moderately with three occurrences, and very few with four and five occurrences. Thus, these findings help in enhancing the quality of data for better analytics.

In the radio frequency (RF) front-end, LNA with good noise figure without degrading performance a very important component to be developed. This paper presents design of two topologies of current reuse based Low Noise Amplifier (LNA) with low noise figure. LNA1 describe the fully integrated narrow band Differential Merged LNA-Mixer (DMLNAM) with two current reuse paths and LNA2 describes fully integrated Two stage Dual Band Low Noise Amplifier (DB-LNA) for 1.8GHz and 2.4GHz with two gain modes (high gain mode, low gain mode) in 65nm technology. The proposed DMLNAM(LNA1) employ first current reuse path to achieve low power, high gain and low noise figure and second current reuse path for narrow band load tuning and gm stage of Mixer is stacked on the top of CMOS LNA. In the proposed Two stage DB-LNA(LNA2), first stage employs a varactor for dual band input matching with self-biasing technique, current reuse structure to achieve high gain, low noise figure and low power consumption. Second stage employs current splitting technique to switch between two gain modes. Differential Merged LNA-Mixer features gain of 26.64dB with noise figure of 1.61dB@10MHz, 1.62dB@1MHz and 1.77dB@100KHz. In high gain mode (SW1=0V) of Two-stage Dual band LNA(LNA2) with two gain modes have a gain of 21.1dB, 19.61dB with a noise figure of 1.739dB, 2.22dB at 1.8GHz and 2.4GHz respectively. In low gain mode (SW1=1.2V), the Two stage DB-LNA features a gain of 12.15dB and 10.6dB and a noise figure of 2.36dB and 3.51dB at 1.8GHz and 2.4GHz respectively. The DMLNAM (LNA1) and Two stage DB-LNA circuit consumes 16.5mW@1.5V and 11mW@1.2V respectively.

Cyclic Redundancy check (CRC) is primarily used in the physical layer of transmission protocols (viz., Ethernet and Bluetooth). CRC computation can be done in two ways; either serial computation or parallel computation. CRC computation implement linear feedback shift registers (LFSRs). The proposed paper gives an insight of serial and parallel implementation of CRC 8- CCITT widely used in Header Error Control in Asynchronous Transfer Mode (ATM HEC).

The main disorder of unilateral facial paralysis patients is loss of blink in paralyzed side eye. Functional electrical stimulation (FES) is considered to be one of the promising techniques for recovery of blink. The levels of electrical stimulus required for blink differs from patient to patient based on Electrode-Tissue Impedance (ETI). Hence, the motivation of the present work is to design a programmable stimulator which can accommodate wide range of current stimulus levels suitable for wide variety of patients. The present work targets 8 levels of chopped bi-phasic current stimulation levels ranging from 0.33 mA to 1.51 mA. This architecture is designed with two modes of operation, normal and programmable modes. In normal mode, a trigger signal is required from blink detection circuit from the healthy side. However, in programmable mode, the programmability of different stimulus levels was achieved by an external device with 6 bits of data. In this receiver frontend, Envelope Detector (ED) is stacked on Low Noise Amplifier (LNA) for reusing current with low power. A 3 bit latch is designed to hold current level bits which can program through 6 bit shift register. Switch control logic is designed using a Linear Feedback Shift Register (LFSR) and an AND gate. The proposed architecture in this work is designed with UMC 180 nm CMOS technology. Current reuse LNA and ED features gain of 12.13 dB@2.4 GHz with a noise figure(NF) of 6.77 dB@2.4 GHz and S11 of -18 db@2.4 GHz. Current Stimulator circuit can provide a chopped bi-phasic current pulse which ranges from 336 μA up to 1.5 mA for a wide range of Electrode Orbicularis Oculi muscle impedance, Rs=0.1kΩ to 2kΩ, Cp=1nF to 5nF. Current consumption during non-blink, re-programmable and blink trigger are 22.5 μA,37.5 μA and 362 μA to 1.51 mA respectively.