The proliferation of new technologies and advancements in existing ones are altering our perspective of the world. So, continuous improvements are needed. A connected world filled with a vast amount of data was created as a result of the integration of these advanced technologies in the financial sector. The advantages of this connection came at the cost of more sophisticated and advanced attacks, such as fraudulent transactions. To address these illegal transactions, researchers and engineers have created and implemented various systems and models to detect fraudulent transactions; many of them produce better results than others. On the other hand, criminals change their strategies and technologies to imitate legitimate transactions. In this article, the objective is to propose an intelligent system for detecting fraudulent transactions using various deep learning architectures, including artificial neural networks (ANNs), recurrent neural networks (RNNs), and long short-term memory (LSTM). Furthermore, the Bayesian optimization algorithm is used for hyperparameter optimization. For the evaluation, a credit card fraudulent transaction dataset was used. Based on the many experiments conducted, the RNN architecture demonstrated better efficiency and yielded better results in a shorter computational time than the ANN LSTM architectures.

A decentralized service placement policy plays a key role in distributed systems, such as fog computing, where sharing workloads fairly among active computing nodes is critical. A decentralized policy is an inherent feature of the service placement process that may improve load balancing among computers and can reduce the latency in many real‐time Internet of Things (IoT) applications. This article proposes reinforcement optimization for a decentralized service placement policy, which attempts to mitigate some of the drawbacks of existing service placement policies. Matching task size with node specifications and the allocation of less popular but time‐sensitive applications in the fog layer are the primary contributions of this study. Extensive experimental comparisons are made between the proposed algorithm and other well‐known algorithms over service latency, network usage, and computing usage using the iFogSim simulator. A microservice‐based application with varying sizes of computing requests are tested experimentally and show that the proposed algorithm effectively serves computing instances that are closer to users, reducing service latency and network usage. Compared to the existing models, the proposed modified algorithm reduces service latency by 24.1%, network usage by 4%, and computing usage by 20%, thus highlighting positive outcomes when using the proposed algorithm for fog analytics in future real‐time IoT applications.

Load balancing is crucial in distributed systems like fog computing, where efficiency is paramount. Offloading with different approaches is the key to balancing the load in distributed environments. Static offloading (SoA) falls short in heterogeneous networks, necessitating dynamic offloading to reduce latency in time-sensitive tasks. However, prevalent dynamic offloading (PoA) solutions often come with hidden costs that impact sensitive applications, including decision time, networks congested and distance offloading. This paper introduces the Hybrid Offloading (HybOff) algorithm, which substantially enhances load balancing and resource utilization in fog networks, addressing issues in both static and dynamic approaches while leveraging clustering theory. Its goal is to create an uncomplicated low-cost offloading approach that enhances IoT application performance by eliminating the consequences of hidden costs regardless of network size. Experimental results using the iFogSim simulation tool show that HybOff significantly reduces offloading messages, distance, and decision-offloading consequences. It improves load balancing by 97%, surpassing SoA (64%) and PoA (88%). Additionally, it increases system utilization by an average of 50% and enhances system performance 1.6 times and 1.4 times more than SoA and PoA, respectively. In summary, this paper tries to introduce a new offloading approach in load balancing research in fog environments.

Credit card fraud detection is a critical task in financial systems, requiring effective algorithms to accurately classify transactions as fraudulent or non-fraudulent. This paper proposes a novel approach, combining the AdaBoost algorithm with Long Short-Term Memory (LSTM) networks, called the AdaBoost-LSTM algorithm, to improve the detection of fraud in sequential transaction data. The AdaBoost algorithm is widely known for its ability to combine multiple weak classifiers into a strong one. In this work, we adapt it to sequential learning tasks by leveraging Long Short-Term Memory (LSTM) networks, which effectively capture temporal dependencies in transaction data. In this approach, multiple LSTM models are trained sequentially, with each model focusing on the misclassified samples from the previous one. Sample weights are adjusted at each iteration to emphasize hard-to-classify instances, and transfer learning is employed to initialize each new LSTM with the parameters learned from the previous iteration, thus reducing computational costs and overfitting risks. The proposed method is evaluated on a credit card fraud detection dataset, demonstrating its effectiveness in improving classification accuracy compared to traditional models.

Tight output regulation in power converters and electric drive systems requires a control strategy that simultaneously minimizes tracking error and maintains smooth actuation-two objectives that are intrinsically in tension for nonlinear, parameter-varying plants. Despite the widespread deployment of fractional-order PD sliding mode control (FOPD-SMC) and Mamdani fuzzy logic control (FLC) in this domain, no prior study has placed them in a direct, metric-identical comparison on a common plant. The present work closes this gap by implementing both controllers on the same second-order discrete-time nonlinear plant-representative of DC-DC converter output dynamics and motor-drive input-output behavior and evaluating them under a composite reference that combines sinusoidally-modulated ramps with step transitions, scored by the integral of squared error (ISE) and integral of absolute error (IAE). FOPD-SMC achieves ISE= 1.639 × 10-2 and IAE= 3.345 × 10-2, outperforming FLC by 87.6% and 50.4%, respectively; the advantage originates from the non-integer memory embedded in the sliding surface via the Gr¨unwald-Letnikov operator and from the explicit decomposition of the control law into nominal-tracking and robustness components. FLC, conversely, produces a chattering-free, continuously varying control signal a structural consequence of smooth Gaussian membership functions and linguistic rule aggregation, at the cost of a mean absolute tracking error twice that of FOPD-SMC. These findings establish a quantitative selection criterion: FOPD-SMC is recommended when tight voltage or current regulation is the primary objective, while FLC is preferred where smooth torque delivery and reduced actuator stress outweigh marginal gains in tracking accuracy.

Number Theoretic Transform (NTT)-based polynomial multiplication is a computationally intensive operation in lattice-based post-quantum cryptography (PQC) schemes such as CRYSTALS-Dilithium. Existing hardware accelerators optimize area and timing performance, without focusing on evaluating trade-offs among hardware utilization, execution latency, operating frequency, and power consumption. This article investigates such trade-offs through two lightweight field-programmable gate array (FPGA) implementations of an iterative NTT-based polynomial multiplication accelerator, namely non-pipelined and 4-stage pipelined architectures. Both implementations employ a single butterfly unit based on Cooley–Tukey and Gentleman–Sande configurations to compute the forward NTT (FNTT), inverse NTT (INTT), and coefficient-wise multiplication (CWM). The 4-stage pipelined architecture employs pipeline registers in the modular multiplication and Barrett reduction datapaths to maximize the operating frequency. Both architectures are implemented on an Artix-7 FPGA and evaluated across operating frequencies ranging from 10 MHz to 280 MHz. The results show that the non-pipelined architecture provides reduced hardware overhead and lower power consumption, whereas the pipelined architecture improves timing scalability and successfully operates at 280 MHz. At the maximum operating frequency, the pipelined implementation utilizes 1115 slices and achieves execution times of 4.58 μs, $0.93\mathsf{\mu }$s, and $4.58\mathsf{\mu }$s for FNTT, CWM, and INTT computations, respectively, with an average power consumption of 133 mW. The Area–Time Product (ATP) and Energy–Delay Product (EDP) evaluations demonstrate that the pipelined architecture achieves improved overall efficiency within the proposed lightweight single-butterfly-based polynomial multiplication architecture at higher operating frequencies, obtaining an ATP of $7.74\times {10}^3$ Slice-$\mathsf{\mu }$s and EDP of 1501.52 nJ-$\mathsf{\mu }$s.