Modern image processing systems deployed on embedded and heterogeneous platforms face increasing pressure to deliver high performance under strict energy and real-time constraints. The rapid growth in image resolution and frame rates has significantly amplified computational demand, making uniform full-precision processing increasingly inefficient. This paper presents a significance-driven adaptive approximate computing framework that reduces energy consumption by tailoring computational precision and resource allocation to the spatial importance of image content. We introduce a statistical importance metric that captures local structural variability using low-complexity deviation-based analysis on luminance information. The metric serves as a lightweight proxy for identifying regions that are more sensitive to approximation errors, enabling differentiated processing without the overhead of semantic or perceptual saliency models. Based on this importance classification, the proposed framework dynamically orchestrates heterogeneous CPU-GPU resources, applies variable kernel sizes, and exploits dynamic voltage and frequency scaling (DVFS) to reclaim timing slack for additional energy savings. The framework is validated through two complementary case studies: (i) a heterogeneous software implementation for adaptive convolution filtering on an Odroid XU-4 embedded platform, and (ii) a hardware-level approximate circuit allocation approach using configurable-precision arithmetic units. Experimental results demonstrate energy reductions of up to 60% compared to uniform-precision baselines, while maintaining acceptable visual quality. Image quality is evaluated using both PSNR and the perceptually motivated SSIM metric, confirming that the proposed approach preserves structural fidelity despite aggressive approximation.

Energy efficiency has become a primary bottleneck in hardware platforms supporting machine learning workloads, particularly as modern inference and training tasks demand sustained high-throughput computation. This challenge is further amplified in energy-harvesting and intermittently powered systems, where the available energy budget varies over time. This work introduces a run-time configurable multiply–accumulate (MAC) architecture that dynamically adjusts arithmetic precision to match instantaneous energy availability. The proposed design relies on an internally adaptive multiplier based on bit-level logic compression, enabling controlled modulation of power consumption while preserving numerical robustness. Crucially, the MAC maintains a fixed external operand interface, allowing for seamless precision adaptation without operand reformulation or datapath disruption. The architecture is implemented in System Verilog and evaluated using both ASIC synthesis in a 90 nm CMOS technology and FPGA deployment. Experimental results demonstrate approximately a fourfold improvement in power–delay product (PDP) relative to full-precision operation, with only limited degradation in inference accuracy.