Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semiconductor supply chain, which has established a worldwide span to reduce costs, time to market, and increase productivity. Recently, integrated circuits (ICs) counterfeiting has threatened systems security and reliability that utilize ICs in all domains. This article focuses on the most counterfeited area—recycled and remarked ICs—and aims to develop a technique to distinguish between new and used digital ICs based on an aging sensor mechanism. Aging sensors have been studied based on path-delay fingerprinting and ring oscillators (ROs) frequency degradation, but their resolution requires further development to accurately detect short usage. This study proposes a novel differential aging sensor to measure the discharge time ( $\tau {{{dv}}}$ ) increase that depends on the subthreshold leakage current due to aging with two on-chip designs. Simulations were conducted using the GlobalFoundries (GF) 22 nm for aging with bias temperature instability and hot carrier injection (HCI) combined. The results show that the $\tau {{{dv}}}$ increase is 14.72% after 15 days of usage and increases to 60.49% after three years. This further increases at higher temperatures; the highest simulated temperature ( $125~^{\circ }\text{C}$ ) $\tau {{{dv}}}$ increases by 55.93% after 15 days and 310.17% after three years. The proposed method also outperformed the traditional frequency degradation-based aging estimation method, which at nominal temperature is found to be 5.00% after 15 days and 23.68% after three years. Therefore, discharge time is a sensitive indicator for aging, surpasses frequency in detecting previous usage and is robust against process, voltage, and temperature variations (PVTs).

The semiconductor supply chain industry is spread worldwide to reduce costs and meet the high demand for integrated circuits (ICs) in electronic systems. The high utilisation of electronic devices in the next decade is forecasted to reach trillions, increasing the already high volume of e-waste. It will lead to concerns about the security and reliability of ICs, particularly those exposed to counterfeiting, i.e., recycled and remarked ICs. This paper harvests aging degradation induced by bias temperature instability (BTI) and hot carrier injection (HCI), observing frequency (f) and discharge time (τdv) affected by changes in drain current and sub-threshold leakage current over the lifetime of an IC to estimate the IC age. This is carried out using Cadence simulations, implementing 13- and 51-stage ring oscillators (ROs) using a 22-nm CMOS technology and aging model provided by GlobalFoundries (GF). The machine learning (ML) algorithm of support vector regression (SVR) is adapted for this application, using a training process that involves operating temperature, τdv, f, aging time and inter-die and intra-die process variation (PV). The data sampling is performed over a simulated 12-year period with representative temperatures between 20°C up to 100°C and with additional testing data from 25°C up to 75°C. Incorporating the PV effect with the SVR model allows the proposed SVR model to be adopted in practical IC implementation. The results demonstrate high accuracy in aging estimation by SVR with/without PV effects. The proposed SVR model detects the age of an IC with an error accuracy between 0.206 and 0.667 (deviation of 74.16 and 240.12 days), and 0.091 and 0.237 (deviation of 32.76 and 85.32 days) based on the Root Mean Square Error (RMSE) for 13- and 51-satge RO, respectively. It outperforms the state-of-the-art IC age prediction models even when learning and validating the model with aging and PV.

Energy efficiency has become a primary bottleneck in hardware platforms supporting machine learning workloads, particularly as modern inference and training tasks demand sustained high-throughput computation. This challenge is further amplified in energy-harvesting and intermittently powered systems, where the available energy budget varies over time. This work introduces a run-time configurable multiply–accumulate (MAC) architecture that dynamically adjusts arithmetic precision to match instantaneous energy availability. The proposed design relies on an internally adaptive multiplier based on bit-level logic compression, enabling controlled modulation of power consumption while preserving numerical robustness. Crucially, the MAC maintains a fixed external operand interface, allowing for seamless precision adaptation without operand reformulation or datapath disruption. The architecture is implemented in System Verilog and evaluated using both ASIC synthesis in a 90 nm CMOS technology and FPGA deployment. Experimental results demonstrate approximately a fourfold improvement in power–delay product (PDP) relative to full-precision operation, with only limited degradation in inference accuracy.