Jingfang Wang

Prof. Jingfang Wang

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Academic Career Length

36Years (1991-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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28 April 2016 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
SYShiyan Yang
Shiyan Yang
JWJingfang Wang
Jingfang Wang
WYWei Yang
Wei Yang
A simple and robust 24-pulse diode rectifier for low-voltage and high-current applications is proposed in this paper. The proposed 24-pulse diode rectifier consists of a conventional four-star 12-pulse diode rectifier and an auxiliary single-phase full-wave rectifier (ASFR) installed at dc side. The low-power (3.4%Po) ASFR extracts two rectangular currents from the modified second-stage interphase transformer and injects a square current into the output of the rectifier system. This modification extends the conventional four-star 12-pulse operation to 24-pulse operation. The proposed 24-pulse rectifier draws near sinusoidal input line currents with the absence of 5th, 7th, 11th, 13th, 17th, and 19th harmonics. The average value of current through the ASFR has only 1.7% of load current, which means the current rating and conduction losses of ASFR are very small. The proposed scheme has low-diode conduction losses, and it is more suitable for low-voltage and large-current applications. Since only an additional ASFR is needed, the proposed scheme is low cost and simple to implement. The detailed analysis for the proposed rectifier is presented, and experimental results are provided to verify the proposed concept.
1 December 2020 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
JWJingfang Wang
Jingfang Wang
XYXuliang Yao
Xuliang Yao
XGXu Gao
Xu Gao
SYShiyan Yang
Shiyan Yang
A simple and robust harmonics reduction scheme for 12-pulse diode rectifier using two auxiliary single-phase full-wave rectifiers (ASFRs) is proposed in this paper. The two ASFRs are installed at dc side of the rectifier. One ASFR is connected in series with the load to directly modulate the output current of double star rectifiers, whereas another ASFR is connected in parallel with the load to indirectly shape the output current of double star rectifiers. The coadjutant modulation of the two ASFRs increases the output current states of double star rectifiers first, thereby increasing the number of steps in the input line currents. This modidication extends the conventional 12-step input line current to a 36-step input line current. The proposed rectifier draws near sinusoidal input line currents with the absence of 11th, 13th, 23th and 25th harmonics. Since only two ASFRs are sufficient, the proposed rectifier is completely passive and has the least number of component count, making it robust and simple to implement. Analytical results are experimentally verified on 1.8 kW experimental rectifiers.
18 August 2020 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Verified
Journal Article
Closed access
JWJingfang Wang
Jingfang Wang
XYXuliang Yao
Xuliang Yao
JBJingshi Bai
Jingshi Bai
XGXu Gao
Xu Gao
SYShiyan Yang
Shiyan Yang
A simple and robust 36-pulse diode rectifier which consists of a conventional 12-pulse rectifier and a hybrid pulse multiplication interphase reactor (HPM-IPR) is proposed in this article. The HPM-IPR includes a modified interphase reactor (M-IPR), an auxiliary single-phase full-bridge rectifier (ASFBR), and an auxiliary single-phase full-wave rectifier (ASFWR). The ASFBR is connected in series with the load to modulate the output current of the rectifier bridges directly. The ASFWR is connected in parallel to shape the output current of the rectifier bridges indirectly. The conjoint modulation of ASFWR and ASFBR significantly increases the number of output current states of the rectifier bridge, which in turn extends the conventional 12-pulse operation to 36-pulse operation. The proposed 36-pulse diode rectifier draws near the sinusoidal input line currents with THD less than 5%. The kVA ratings of ASFBR and ASFWR are only 1.1% and 1.8% of the output power of the proposed rectifier, respectively, which indicates that the proposed method is suitable for high-power industrial applications. Since only one ASFWR and one ASFBR are adequate, the proposed scheme is low cost, highly reliable, and simple. The detailed analysis is presented, and some experimental results are provided to verify the proposed method.
10 January 2022 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
JWJingfang Wang
Jingfang Wang
ACAnchen Chen
Anchen Chen
XYXuliang Yao
Xuliang Yao
LLLei Li
Lei Li
YLYusheng Lv
Yusheng Lv
QCQiming Chen
Qiming Chen
A simple 24-pulse rectifier that provides low-harmonic utility power interface is proposed in this article. The proposed 24-pulse rectifier consists of a 12-pulse rectifier using a zigzag phase-shifting transformer and an auxiliary pulse-doubling circuit (APDC). Two auxiliary diodes in the APDC extract specific rectangular currents from the dc side of the rectifier to modulate and increase the output states of three-phase rectification bridges first, and then the 12-pulse rectifier is extended to a 24-pulse rectifier in accordance with the current relationship between ac and dc sides. The main low-order harmonics, such as 11th and 13th, are reduced markedly from the input line current and the proposed rectifier draws near-sinusoidal input line currents with less than 5% THD from the utility. The maximum current flowing through the two auxiliary diodes in APDC is only 3.4% of the load current and the capacity of APDC is only 3.06% of the output power. Thus, the proposed scheme is inexpensive and easy to implement and has a simple circuit configuration. Theoretical analyses were experimentally verified using a 1.7-kW experimental prototype.
15 February 2022 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
JWJingfang Wang
Jingfang Wang
ACAnchen Chen
Anchen Chen
LLLei Li
Lei Li
CZChen Zhao
Chen Zhao
XYXuliang Yao
Xuliang Yao
QCQiming Chen
Qiming Chen
A series-connected 36-pulse rectifier with passive pulse-tripling circuit (PPTC) on the dc side is proposed in this article. The proposed rectifier consists of a series-connected 12-pulse rectifier and a PPTC. The PPTC includes a passive current forming network, a single-phase auxiliary transformer with dual secondary windings and two auxiliary single-phase rectifiers (ASRs). One ASR in PPTC is connected in series with the load to directly modulate the output current of rectifier bridges. The other ASR in PPTC is connected in parallel with the load to modulate the output current of rectifier bridges according to the relationship between its input voltage and load voltage. Composite modulation of the two ASRs increases the pulse number of the rectifier from 12 pulses to 36 pulses. The resulting rectifier obtains an approximate sinusoidal input current with less than 5% THD. Only a few low-capacity passive components are sufficient given the absence of active components in the proposed scheme. The proposed scheme presents advantages of simple circuit structure, easy implementation, and high reliability. Detailed analysis and experimental results are provided to verify the effectiveness of the proposed scheme.
19 December 2022 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Verified
Journal Article
Closed access
XYXuliang Yao
Xuliang Yao
SHShengqi Huang
Shengqi Huang
JWJingfang Wang
Jingfang Wang
HMHe Ma
He Ma
GZGuowang Zhang
Guowang Zhang
YWYujian Wang
Yujian Wang
This paper presents a sensorless finite control set model predictive current control (FCS-MPCC) for surface-mounted permanent magnet synchronous motor drives based on an improved reduced-order generalized integrator-frequency-locked loop (IROGI-FLL). To simplify the structure of the sensorless FCS-MPCC and avoid control performance degradation caused by the rotor position estimation error, an instantaneous power theory-based given current calculation method is designed. Accordingly, the whole algorithm can be realized without using rotor position. IROGI-FLL is adopted for filtering the estimated back electromotive force and estimating motor speed. To enhance its dynamic speed tracking performance, a speed tracking deviation compensation term is designed for FLL. With the feedforward compensation term, speed static tracking deviation in acceleration and deceleration states can be eliminated. Moreover, to avoid the adverse effect of parameter mismatch on control performance, an incremental adjustable model-based model reference adaptive system (MRAS) is introduced to identify the resistance and inductance parameters. The incremental adjustable model can avoid identification error caused by the rank deficiency issue. Finally, the effectiveness of the proposed method is investigated by experiments.