Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

A new three-dimensional (3D) integration technology to achieve system-on-silicon LSIs has been proposed. Several LSI wafers are vertically stacked and glued each other after thinning them in this 3D integration technology. Therefore, this technology can be considered as both 3D LSI technology and a wafer-scale 3D chip-on-chip packaging technology. Effective packing density can be significantly increased by stacking several chips in the vertical direction. In addition, a huge number of interconnections are formed through these stacked chips. Therefore, the chip-package co-design considering the 3D distribution of generated heat and the 3D routing of wirings becomes very important to realize 3D LSIs or 3D multichip modules (3D-MCMs) using this new integration technology. Various kinds of new system-on-silicon LSIs or system LSIs based on this 3D integration technology have been proposed. A real time microvision system has been described as a typical example of the systems realized by using this new 3D integration technology. Several key technologies for this 3D integration such as formation of buried interconnection and microbump, wafer thinning, wafer alignment and wafer bonding have been described.

Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers. Silicon based packaging and 3D stacked die technologies have been in research studies for more than a decade at IBM and in industry, universities & consortia. IBM research experiments have included test vehicle design, build, characterization and modeling. Robust structures and processes have been developed based on (i) process learning for silicon based structures, (ii) assembly process comparisons for fine pitch chip interconnection, (iii) electrical, mechanical and thermal characterization and (iv) reliability & accelerated stress characterization. TSV technology investigations have included composite, copper and tungsten metallurgies. Wiring demonstrations ranged from sub-micron fine pitch wiring line widths & spaces to larger dimensions. I/O interconnections investigated feature sizes such as 100 I/O / mm², 400 I/O/mm², and interconnection features sizes which support 2500 I/O / mm². In addition, integrated decoupling capacitors of one hundred ten nano-farads per mm² per layer and assembly of module structures on silicon packages with ceramic or organic base packages were demonstrated. Examples of robust TSV structures and characterization, single die with silicon interposers, multiple die on a silicon package and stacked die assemblies are given along with highlights of characterization including aspects of electrical, mechanical and reliability results. This research paper describes recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures. In addition, examples of potential applications that may take advantage of 3D integration are discussed.

In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed. Unlike standard 100-micron C4 solder balls, very small solder volumes (<6 microns high) were investigated. The mechanical properties were evaluated by shear and impact shock testing, while scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the IMC layers in solder joins before and after annealing. It was found that Cu/Ni/In and Cu/In interconnections have slightly lower shear strength per bump. While these values were lower than the Cu/Sn joins, the Cu/Ni/In chips passed the impact shock test for a simulated heat sink mass of 27g/cm ² . The reasons for the differences in reliability of these metallurgies are discussed. 3D chip stacking using two-layers of chips with fine-pitch lead-free interconnects was demonstrated. The resistance of link chains comprising through-vias, lead-free interconnects and Cu links were measured using a 4-point probing method. The average resistance of the through-via including the lead-free interconnect was 21mΩ.

A new three-dimensional (3D) integration technology based on wafer bonding technique has been proposed for intelligent image sensor chip with 3D stacked structure. We have developed key technologies for such 3D integration. A 3D image sensor test chip was fabricated using this 3D integration technology. Basic electric characteristics were evaluated in the 3D image sensor test chip.