The past two decades have witnessed the stagnation of the clock speed of microprocessors followed by the recent faltering of Moore’s law as nanofabrication technology approaches its unavoidable physical limit. Vigorous efforts from various research areas have been made to develop power-efficient and ultrafast computing machines in this post-Moore’s law era. With its unique capacity to integrate complex electro-optic circuits on a single chip, integrated photonics has revolutionized the interconnects and has shown its striking potential in optical computing. Here, we propose an electronic-photonic computing architecture for a wavelength division multiplexing-based electronic-photonic arithmetic logic unit, which disentangles the exponential relationship between power and clock rate, leading to an enhancement in computation speed and power efficiency as compared to the state-of-the-art transistors-based circuits. We experimentally demonstrate its practicality by implementing a 4-bit arithmetic logic unit consisting of 8 high-speed microdisk modulators and operating at 20 GHz. This approach paves the way to future power-saving and high-speed electronic-photonic computing circuits.

In recent decades, the demand for computational power has surged, particularly with the rapid expansion of artificial intelligence (AI). As we navigate the post-Moore's law era, the limitations of traditional electrical digital computing, including process bottlenecks and power consumption issues, are propelling the search for alternative computing paradigms. Among various emerging technologies, integrated photonics stands out as a promising solution for next-generation high-performance computing, thanks to the inherent advantages of light, such as low latency, high bandwidth, and unique multiplexing techniques. Furthermore, the progress in photonic integrated circuits (PICs), which are equipped with abundant photoelectronic components, positions photonic-electronic integrated circuits as a viable solution for high-performance computing and hardware AI accelerators. In this review, we survey recent advancements in both PIC-based digital and analog computing for AI, exploring the principal benefits and obstacles of implementation. Additionally, we propose a comprehensive analysis of photonic AI from the perspectives of hardware implementation, accelerator architecture, and software-hardware co-design. In the end, acknowledging the existing challenges, we underscore potential strategies for overcoming these issues and offer insights into the future drivers for optical computing.

Due to the projected saturation of Moore’s law, as well as the drastically increasing trend of bandwidth with lower power consumption, silicon photonics has emerged as one of the most promising alternatives that has attracted a lasting interest due to the accessibility and maturity of ultra-compact passive and active integrated photonic components. In this Letter, we demonstrate a ripple-carry electro-optic 2-bit full adder using microdisks, which replaces the core part of an electrical full adder by optical counterparts and uses light to carry signals from one bit to the next with high bandwidth and low power consumption per bit. All control signals of the operands are applied simultaneously within each clock cycle. Thus, the severe latency issue that accumulates as the size of the full adder increases can be circumvented, allowing for an improvement in computing speed and a reduction in power consumption. This approach paves the way for future high-speed optical computing systems in the post-Moore’s law era.

Photonic integrated circuits (PICs) with compact size and low power consumption have opened the possibility of realization of ultrahigh-speed and energy-efficient optical computing in an integrated system that may be comparable to CMOS-based electrical integrated circuits in many aspects. Directed logic is an innovative paradigm that can make full use of the advantages of electronics and photonics for optical computing. In this paper, we propose various designs of directed-logic-based electro-optic ripple-carry adders in integrated silicon photonics, which replace the electrical components in the critical path using optical counterparts. All control signals are applied simultaneously through ultralow-power microdisk modulators so that the propagation delay could be reduced significantly. A two-bit thermal-optic full adder based on microdisk modulators is demonstrated as a proof of concept along with a projection of high-speed performance. The proposed electro-optic full adder paves the way to future low-power-consumption and large-bandwidth optical computing in integrated silicon photonics.

As a promising neuromorphic framework, the optical neural network (ONN) demonstrates ultra-high inference speed with low energy consumption. However, the previous ONN architectures have high area overhead which limits their practicality. In this paper, we propose an areaefficient ONN architecture based on structured neural networks, leveraging optical fast Fourier transform for efficient computation. A two-phase software training flow with structured pruning is proposed to further reduce the optical component utilization. Experimental results demonstrate that the proposed architecture can achieve 2.2 3.7× area cost improvement compared with the previous singular value decompositionbased architecture with comparable inference accuracy. A novel optical microdisk-based convolutional neural network architecture with joint learnability is proposed as an extension to move beyond Fourier transform and multi-layer perception, enabling hardware-aware ONN design space exploration with lower area cost, higher power efficiency, and better noiserobustness.

Integrated optical computing has the potential to enhance the computation abilities in terms of computing speed and power consumption during the post-Moore's law era. As one of the widely investigated approaches, electro-optic logic uses electro-optic switches as the building blocks to achieve complex functions. In this paper, we propose and experimentally demonstrate a multioperand electro-optic logic gate that contains multiple active regions in a single gate to further increase the versatility of gates. Thus, one gate can be controlled by several electrical inputs simultaneously. The ability of multioperand logic gates is thoroughly explored. The detailed comparison shows that the proposed gate can largely improve the circuit performance in terms of the area, latency, power, and insertion loss. We believe the multioperand logic gate has the potential to contribute to a more compact and power-efficient integrated optical computing system.