In this letter, we present a 24-GSa/s, >20-GHz wideband track-and-hold amplifier (THA) based on indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology for high-speed sampling systems. In the proposed approach, the output pole of the input stage is canceled by the zero produced by the emitter capacitive/resistive degeneration, and the bandwidth is thereby extended without voltage drop. The compensation technique for Vbe modulation in the output stage is introduced to reduce distortion. The monolithic microwave integrated circuit (MMIC) prototype occupies only 0.69 mm², and the experimental results show that it has a 0.112-fT bandwidth from dc to 22.3 GHz, which is wider than any ratio reported compact THA solutions using the InP technology. In addition, a spurious-free dynamic range (SFDR) of better than 42 dB and total harmonic distortion (THD) of less than -25 dBc are demonstrated at a 24-GSa/s sampling rate. The THA consumes only 374 mW, which is among the lowest dc power dissipation reported for the InP technology.

This paper presents a modular technology for two-stage broadband power amplifier (PA) design. The proposed method focuses on separately realizing two stage’s flat gain characteristics, thus providing the entire circuit’s required flatness over broad bandwidth. The power stage employs stacked structure to provide enough power and confine the output impedance around $50~\Omega $ , while the driver stage’s periphery is selected to achieve impedance transformation demanded by modularization. The elaborate requirements for input and inter-stage matching networks (MNs) are repeatable which can be synthesized by real frequency technique (RFT), shortening the design time of broadband MNs. The modular approach can also be transferred to the implementation of other broadband PAs. This novel technology was verified using $0.25~\mu \text{m}$ GaAs PHEMT process. The fabricated two-stage broadband PA obtains a small-signal gain higher than 35.0 dB and saturated output power of 37.2± 1.6 dBm from 30 MHz to 2.7 GHz, with a peak power added efficiency (PAE) of 46.2% at 500 MHz. To our knowledge, this is the highest gain and output power in GaAs broadband amplifier below 2.7 GHz.

This paper reports a manufacturable process of 0.18 micron SiGe BiCMOS integrating novel structure SiGe HBTs and 0.18 micron foundry-compatible CMOS devices. N-type SiGe HBT is newly designed by removing deep trench isolation, N+ sink collector pick-up and collector epitaxial growth. Instead, junction isolation, collector pick-up of deep contact through field oxide and implanted collector are used in SiGe HBT. The peak fT and fmax of N-type high speed SiGe HBT are 120GHz and 110GHz, respectively and the size of SiGe HBT is only half as conventional one. CMOS front-end process steps except P+ source/drain implants and RTA are prior to that of SiGe HBTs to minimize the impact of CMOS thermal budgets on SiGe HBT.

Stacked structure is a good solution to overcome the low output voltage swing provided by a single device. When several devices are stacked, the bandwidth and output power are multiple times higher. This article analyzes the small‐signal voltage gain of the stacked structure, deriving the gain expression of the high‐frequency model and simplified model. Based on the specific device parameter, the different small‐signal voltage gains between the two models are compared and the designed stacked structure is proved to obtain a flat gain at low frequencies below about 3 GHz. To our best knowledge, this is the first article to analyze the gain flatness of stacked structure with two equivalent circuit models. To verify the stacked theory, a pseudomorphic high‐electron‐mobility transistor（PHEMT） power amplifier (PA) is implemented using 0.25 μm Gallium arsenide (GaAs) technology. The PA achieves an ultra‐high bandwidth of 30 MHz to 3 GHz and a linear gain of 21 dB ± 1.5 dB. At a 16‐V drain bias voltage, a saturated output power of higher than 2 W and a peak power‐added efficiency (PAE) of 44.1% are attained.