This article describes a discrete-time zoom analog-to-digital converter (ADC) intended for audio applications. It uses a coarse 5-bit SAR ADC in tandem with a fine third-order delta-sigma modulator (Δ Σ M) to efficiently obtain a high dynamic range. To minimize its over-sampling ratio (OSR) and, thus, its digital power consumption, the modulator employs a 2-bit quantizer and a loop filter notch. In addition, an extra feed-forward path minimizes the leakage of the SAR ADC's quantization noise into the audio band. The prototype ADC occupies 0.27 mm² in a 0.16-μm technology. It achieves 109.8-dB DR, 106.5-dB SNDR, and 107.5-dB SNR in a 20-kHz bandwidth while dissipating 440 μW. It also achieves state-of-the-art energy efficiency, as demonstrated by a Schreier FoM of 186.4 dB and an SNDR FoM of 183.6 dB.

This paper presents a dynamic zoom analog-to-digital converter for use in low-bandwidth (<1 kHz) instrumentation applications. It employs a high-speed asynchronous successive approximation register (SAR) ADC that dynamically updates the references of a fully differential Δ Σ ADC. Compared to previous zoom ADCs, faster reference updates relax the loop filter requirements, thus allowing the adoption of energy-efficient amplifiers. Fabricated in a 0.16-μm CMOS process, the prototype occupies 0.26 mm² and achieves 119.1-dB peak signal-to-noise ratio (SNR), 118.1-dB peak signal-to-noise-and-distortion-ratio (SNDR), and 120.3-dB dynamic range (DR) in a 1-kHz bandwidth while consuming 280 μW. This results in a Schreier figure of merit (FoM) of 185.8 dB.

This article presents a continuous-time zoom analog to digital converter (ADC) for audio applications. It employs a high-speed asynchronous SAR ADC that dynamically updates the references of a continuous-time delta-sigma modulator (CTDSM). Compared to previous switched-capacitor (SC) zoom ADCs, its input impedance is essentially resistive, which relaxes the power dissipation of its reference and input buffers. Fabricated in a 160-nm CMOS process, the ADC occupies 0.27 mm² and achieves 108.1-dB peak SNR, 106.4-dB peak signal to noise and distortion ratio (SNDR), and 108.5-dB dynamic range in a 20-kHz bandwidth while consuming 618 μW. This results in a Schreier figure of merit (FoM) of 183.6 dB.

In chopper amplifiers, the interaction between the input signal and the chopper clock can give rise to intermodulation distortion (IMD). This chopper-induced IMD is mainly due to amplifier delay, which causes large pulses at the output of the amplifier’s output chopper. This article proposes the use of a so-called fill-in technique to eliminate these pulses, and thus the resulting IMD, by multiplexing the outputs of two identical amplifiers that are chopped in quadrature. A prototype chopper-stabilized amplifier was implemented in a 180-nm CMOS process. Measurements show that the fill-in technique suppresses chopper-induced IMD by 28 dB, resulting in an IMD of −126 dB for input frequencies near 4 $F_{\mathrm {CH}}$ (=80 kHz). It also improves the amplifier’s two-tone IMD (with 79 and 80 kHz inputs) from −97 to −107 dB, which is the same as that obtained without chopping.

This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of -107.8 dB/-102 dB and a peak efficiency of 91%/87% with 8- and 4-Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.