This article presents a fully dynamic scalable switched-capacitor delta-sigma modulator that achieves a 94.1-dB dynamic range (DR). Power-and- bandwidth scalability by only changing the clock frequency is achieved using a capacitively biased and swing-enhanced floating inverter operational transconductance amplifier (OTA). Fabricated in a 180-nm CMOS process, the prototype achieves an signal-to-noise-and-distortion ratio (SNDR) of >87 dB across 4x scaling from 100 to 400 kHz of the sampling frequency $f_{{S}}$ . At 200-kHz $f_{{S}}$ , it achieves an SNDR/DR of 89.3/94.1 dB while consuming 4 μW, leading to a DR-based Schreier figure of merit (FoM) of 177.1 dB.

Recent years have witnessed an improvement in the energy efficiency of capacitive sensor interfaces by more than three orders of magnitude. This paper reviews the architectural and circuit innovations that have contributed to this progress. The fundamental limit on the energy consumption of capacitive sensor interfaces is discussed, as well as the widely used figure-of-merit (FoM). Interfaces based on period modulation feature simple circuitry, but their power efficiency at higher resolution deteriorates. Those employing ΔΣ modulation achieve high resolution with improved efficiency but require operational transconductance amplifiers that do not easily scale with process and supply voltage. Interfaces using successive approximation techniques feature mostly digital circuitry achieving good power efficiency at medium resolution. To achieve higher resolution, they can also be employed as the front-end in a hybrid architecture, where a back-end based on ΔΣ modulation or a voltage-controlled oscillator (VCO) performs a fine measurement on the front-end’s residue, resulting in high resolution and excellent energy efficiency simultaneously.

This article presents a Class-D audio amplifier for automotive applications. Low electromagnetic interference (EMI) and, hence, smaller LC filter size are obtained by employing a fully differential multilevel output stage switching at 4.2 MHz. A modulation scheme with minimal switching activity at zero input reduces idle power, which is further assisted by a gate-charge reuse scheme. It also achieves high linearity due to the high loop gain realized by a third-order feedback loop with a bandwidth of 800 kHz. The prototype, fabricated in a 180-nm high-voltage BCD process, achieves a minimum THD+N of -107.8 dB/-102 dB and a peak efficiency of 91%/87% with 8- and 4-Ω loads, respectively, while drawing 7-mA quiescent current from a 14.4-V supply. The prototype meets the CISPR 25 Class 5 EMI standard with a 5.7-dB margin using an LC filter with a cutoff frequency of 580 kHz.

A low‐power delta–sigma modulator based on inverter operational‐transconductance amplifiers (OTAs) using correlated level shifting technique (CLS) is presented. The CLS technique boosts the DC gain of inverter‐based OTA from 42 to 79 dB and extends the linear output swing from 55 to 80% of the full scale. Simulation results show that design in 180 nm CMOS technology, the proposed second‐order delta–sigma modulator achieves a signal‐to‐quantisation‐noise ratio improvement of 10.4 dB compared to a conventional inverter‐based modulator implementing the identical loop filter with the same oversampling ratio.

This article presents a 28-W class-D amplifier for automotive applications. The combination of a high switching frequency and a hybrid multibit Δ ΣM-PWM scheme results in high linearity over a wide range of output power, as well as low AM-band EMI. As a result, only a small (150-kHz cutoff frequency), and thus low-cost, LC filter is needed to meet the CISPR-25 EMI average limit (150 kHz-30 MHz) with 10-dB margin. At 28-W output power, the proposed amplifier achieves 91% efficiency while driving a 4-Ω load from a 14.4-V supply. It attains a peak THD+N of 0.00077% (-102.2 dB) for a 1-kHz input signal.

The power supply rejection ratio (PSRR) of conventional differential closed-loop Class-D amplifiers is limited by the feedback and input resistor mismatch and finite common-mode rejection ratio (CMRR) of the operational transconductance amplifier (OTA) in the first integrator. This article presents a 14.4-V Class-D amplifier employing chopping to tackle the mismatch, thereby improving the PSRR. However, chopping-induced intermodulation (IM) within a pulsewidth modulation (PWM)-based Class-D amplifier can severely degrade PSRR and linearity. Techniques to mitigate such IM are proposed and analyzed. To chop the 14.4-V PWM output signal, a high-voltage (HV) chopper employing double-diffused MOS (DMOS) transistors is developed. Its timing is carefully aligned with that of the low-voltage (LV) choppers to avoid further linearity degradation. The prototype, fabricated in a 180-nm BCD process, achieves a PSRR of >110 dB at low frequencies, which remains above 79 dB up to 20 kHz. It achieves a total harmonic distortion (THD) of −109.1 dB and can deliver a maximum of 14 W into an 8- $\Omega $ load with 93% efficiency while occupying a silicon area of 5 mm².